A Pipelined Multi-Core Machine with Operating System Support

Hardware Implementation and Correctness Proof

By: Jonas Oberhauser, Wolfgang J. Paul, Petro Lutsyk

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Paperback | 10 May 2020

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646 Pages

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23.5 x 15.5 x 3.3

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This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. M¼ller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

â¢ MIPS instruction set architecture (ISA) for application and for system programming

â¢ cache coherent memory system

â¢ store buffers in front of the data caches

â¢ interrupts and exceptions

â¢ memory management units (MMUs)

â¢ pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

â¢ local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

â¢ I/O-interrupt controller and a disk

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