Adaptive Techniques for Dynamic Processor Optimization

Theory and Practice

By: Alice Wang (Editor), Samuel Naffziger (Editor)

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Hardcover | 11 June 2008

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The integrated circuit has evolved tremendously in recent years as Moore's Law has enabled exponentially more devices and functionality to be packed onto a single piece of silicon. In some ways however, these highly integrated circuits, of which microprocessors are the flagship example, have become victims of their own success. Despite dramatic reductions in the switching energy of the transistors, these reductions have kept pace neither with the increased integration levels nor with the higher switching frequencies. In addition, the atomic dimensions being utilized by these highly integrated processors have given rise to much higher levels of random and systematic variation which undercut the gains from process scaling that would otherwise be realized. So these factors--the increasing impact of variation and the struggle to control power consumption--have given rise to a tremendous amount of innovation in the area of adaptive techniques for dynamic processor optimization. The fundamental premise behind adaptive processor design is the recognition that variations in manufacturing and environment cause a statically configured operating point to be far too inefficient. Inefficient designs waste power and performance and will quickly be surpassed by more adaptive designs, just as it happens in the biological realm. Organisms must adapt to survive, and a similar trend is seen with processors - those that are enabled to adapt to their environment, will be far more competitive.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Electronic Devices & Materials Microprocessors Computing & I.T.Computer Science Circuits & Components Energy Technology & Engineering Electrical Engineering Mathematics

Optimisation Linear Programming Mechanical Engineering & Materials Mechanical Engineering

Technology Challenges Motivating Adaptive Techniques	p. 1
Introduction	p. 1
Motivation for Adaptive Techniques	p. 2
Components of Power	p. 2
Relation Between Frequency and Voltage	p. 2
Control Loop Implementation	p. 4
Practical Considerations	p. 4
Impact of Temperature and Supply Voltage Variations	p. 7
Technology Issues Relating to Performance-Enhancing Techniques	p. 9
Threshold Voltage Variation	p. 9
Random Dopant Fluctuations	p. 11
Design in the Presence of Threshold Voltage Variation	p. 13
Technology Issues Associated with Leakage Reduction Techniques	p. 14
Practical Considerations	p. 15
Sources of Leakage Current	p. 16
Transistor Design for Low Leakage	p. 20
Conclusion	p. 21
References	p. 21
Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning	p. 25
Adaptive Power Performance Tuning of ICs	p. 25
AVS- and ABB-Scaling Operations	p. 28
Frequency Scaling and Tuning	p. 31
Power and Frequency Tuning	p. 33
Leakage Power Control	p. 37
Performance Compensation	p. 40
Conclusion	p. 44
References	p. 46
Adaptive Circuit Technique for Managing Power Consumption	p. 49
Introduction	p. 49
Adaptive V_DD Control	p. 50
Dynamic Voltage Scaling	p. 50
Frequency and Voltage Hopping	p. 51
Adaptive V_TH Control	p. 55
Reverse Body Bias (VTCMOS)	p. 55
Self-Adjusting Threshold Voltage (SAT) Scheme	p. 55
Leakage Current Monitor	p. 56
V_TH Controllability	p. 57
Device Perspective	p. 59
Forward Body Bias	p. 60
Control Method and Granularity	p. 61
V_TH Control Under Variations	p. 64
V_TH Control vs. V_DD Control	p. 66
Hardware and Software Cooperative Control	p. 68
Cooperation Between Hardware and Application Software	p. 68
Cooperation Between Hardware and Operating System	p. 70
Conclusion	p. 71
References	p. 71
Dynamic Adaptation Using Body Bias, Supply Voltage, and Frequency	p. 75
Introduction	p. 75
Static Compensation with Body Bias and Supply Voltage	p. 76
Adaptive Body Bias	p. 77
Adaptive Supply Voltage	p. 82
Dynamic Variation Compensation	p. 84
Dynamic Body Bias	p. 84
Dynamic Supply Voltage, Body Bias, and Frequency	p. 87
Design Details	p. 87
Measurement Results	p. 89
Conclusion	p. 92
References	p. 92
Adaptive Supply Voltage Delivery for Ultra-Dynamic Voltage Scaled Systems	p. 95
Logic Design for U-DVS Systems	p. 97
Device Sizing	p. 98
Timing Analysis	p. 100
SRAM Design for Ultra Scalable Supply Voltages	p. 101
Low-Voltage Bit-Cell Design	p. 104
Periphery Design	p. 105
Intelligent Power Delivery	p. 107
Deriving V_DD for Given Speed Requirement	p. 107
DC-DC Converter Topologies for U-DVS	p. 109
Linear Regulators	p. 109
Inductor Based DC-DC Converter	p. 109
Switched Capacitor Based DC-DC Converter	p. 110
DC-DC Converter Design and Reference Voltage Selection for Highly Energy-Constrained Applications	p. 112
Minimum Energy Tracking Loop	p. 113
Conclusion	p. 119
References	p. 120
Dynamic Voltage Scaling with the XScale Embedded Microprocessor	p. 123
The XScale Microprocessor	p. 123
Chapter Overview	p. 124
XScale Micro-Architecture Overview	p. 125
Dynamic Voltage Scaling	p. 126
The Performance Measurement Unit	p. 127
Dynamic Voltage Scaling on the XScale Microprocessor	p. 129
Running DVS	p. 130
Impact of DVS on Memory Blocks	p. 134
Guaranteeing SRAM Stability with DVS	p. 134
PLL and Clock Generation Considerations	p. 138
Clock Generation for DVS on the 180 nm 80200 XScale Microprocessor	p. 138
Clock Generation 90 nm XScale Microprocessor	p. 139
Conclusion	p. 142
References	p. 142
Sensors for Critical Path Monitoring	p. 145
Variability and its Impact on Timing	p. 145
What Is a Critical Path	p. 147
Sources of Path Delay Variability	p. 148
Process Variation	p. 149
Environmental Variation	p. 149
Timing Sensitivity of Path Delay	p. 151
Critical Path Monitors	p. 158
Synchronizer	p. 158
Delay Path Configuration	p. 159
Time-to-Digital Conversion	p. 163
Sensitivity	p. 167
Control and Calibration	p. 168
Conclusion	p. 169
Acknowledgements	p. 171
References	p. 171
Architectural Techniques for Adaptive Computing	p. 175
Introduction	p. 175
Spatial Reach	p. 177
Temporal Rate of Change	p. 177
"Always Correct" Techniques	p. 179
Look-up Table-Based Approach	p. 179
Canary Circuits-Based Approach	p. 180
In situ Triple-Latch Monitor	p. 181
Micro-architectural Techniques	p. 182
Error Detection and Correction Approaches	p. 183
Techniques for Communication and Signal Processing	p. 184
Techniques for General-Purpose Computing	p. 186
Introduction to Razor	p. 187
Razor Error Detection and Recovery Scheme	p. 188
Micro-architectural Recovery	p. 190
Recovery Using Clock-Gating	p. 190
Recovery Using Counter-Flow Pipelining	p. 191
Short-Path Constraints	p. 192
Circuit-Level Implementation Issues	p. 192
Silicon Implementation and Evaluation of Razor	p. 195
Measurement Results	p. 196
Total Energy Savings with Razor	p. 197
Razor Voltage Control Response	p. 199
Ongoing Razor Research	p. 200
Conclusion	p. 202
References	p. 203
Variability-Aware Frequency Scaling in Multi-Clock Processors	p. 207
Introduction	p. 207
Addressing Process Variability	p. 209
Approach	p. 209
Combinational Logic Variability Modeling	p. 212
Array Structure Variability Modeling	p. 213
Application to the Frequency Island Processor	p. 215
Addressing Thermal Variability	p. 217
Experimental Setup	p. 218
Baseline Simulator	p. 218
Frequency Island Simulator	p. 219
Benchmarks Simulated	p. 219
Results	p. 220
Frequency Island Baseline	p. 220
Frequency Island with Critical Path Information	p. 221
Frequency Island with Thermally Aware Frequency Scaling	p. 222
Frequency Island with Critical Path Information and Thermally Aware Frequency Scaling	p. 224
Conclusion	p. 225
Acknowledgements	p. 225
References	p. 225
Temporal Adaptation - Asynchronicity in Processor Design	p. 229
Introduction	p. 229
Asynchronous Design Styles	p. 230
Asynchronous Adaptation to Workload	p. 232
Data Dependent Timing	p. 234
Architectural Variation in Asynchronous Systems	p. 237
Adapting the Latch Style	p. 237
Controlling the Pipeline Occupancy	p. 240
Reconfiguring the Microarchitecture	p. 241
Benefits of Asynchronous Design	p. 244
Conclusion	p. 245
References	p. 245
Dynamic and Adaptive Techniques in SRAM Design	p. 249
Introduction	p. 249
Read and Write Margins	p. 250
Voltage Optimization Techniques	p. 251
Column Voltage Optimization	p. 252
Row Voltage Optimization	p. 255
Timing Control	p. 257
Array Power Reduction	p. 259
Sleep Types	p. 259
Active Sleep	p. 260
Passive Sleep	p. 261
P Versus N Sleep	p. 263
Entering and Exiting Sleep	p. 264
Dynamic Cache Power Down	p. 266
Data Bus Encoding	p. 266
Reliability	p. 267
Soft Errors	p. 267
Hard Errors	p. 267
Cache Line Disable	p. 268
Cache Line Remap	p. 268
Defect Correction	p. 268
Conclusion	p. 269
References	p. 270
The Challenges of Testing Adaptive Designs	p. 273
The Adaptive Features of the Itanium 2 9000 Series	p. 273
Active De-skew	p. 273
Cache Safe Technology	p. 277
Foxton Technology	p. 278
The Path to Production	p. 281
Fundamentals of Testing with Automated Test Equipment (ATE)	p. 281
Manufacturing Test	p. 281
Class or Package Testing	p. 283
System Testing	p. 285
The Impact of Adaptive Techniques on Determinism and Repeatability	p. 286
Validation of Active De-skew	p. 287
Testing of Active De-skew	p. 290
Testing of Power Measurement	p. 291
Power Measurement Impacts on Other Testing	p. 294
Test Limitations and Guard-Banding	p. 296
Guard-Band Concerns of Adaptive Power Management	p. 297
Conclusion	p. 300
References	p. 300
Index	p. 303
Table of Contents provided by Ingram. All Rights Reserved.

Adaptive Techniques for Dynamic Processor Optimization

Theory and Practice

At a Glance

Hardcover

Shipping

How to return your order

Defective items

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