Advanced Test Methods for SRAMs

Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

By: Alberto Bosio, Luigi Dilillo, Patrick Girard

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Hardcover | 4 November 2009

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188 Pages

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23.5 x 15.88 x 1.91

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Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called "static faults," but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as "dynamic faults", are not covered by classical test solutions and require the dedicated test sequences presented in this book.

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Published: 3rd September 2014

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Basics on SRAM Testing	p. 1
Overview of Semiconductor Memories	p. 1
Typical Structure of an SRAM	p. 3
The Context of SRAM Testing	p. 5
Memory Model	p. 6
Fault Model Representation	p. 7
Fault Model Classification	p. 8
Test Solutions and Algorithms	p. 12
Test Generation	p. 15
Test Validation	p. 17
Conclusion	p. 19
Resistive-Open Defects in Core-Cells	p. 21
The SRAM Core-Cell	p. 21
Reading in the Core-Cell	p. 21
Writing in the Core-Cell	p. 22
Analysis of Resistive-Open Defects in the Core-Cell	p. 23
Defect Location	p. 23
Defect Incidence Analysis	p. 23
Simulation Set-Up and Results	p. 26
Analysis and Test of dRDF	p. 27
Functional Fault Modeling of dRDF	p. 28
RES: Read Equivalent Stress	p. 29
March Test Solutions Detecting dRDFs	p. 33
Analysis and Test of dDRF	p. 37
Functional Fault Modeling of dDRF	p. 37
Experiments	p. 38
March Test Solution Detecting dDRFs	p. 43
Impact of Technology Scaling	p. 45
Conclusion	p. 48
Resistive-Open Defects in Pre-charge Circuits	p. 49
The SRAM Pre-charge Circuit	p. 49
Analysis of Resistive-Open Defects in the Pre-charge Circuit	p. 51
Defect Location	p. 51
Defect Incidence Analysis	p. 52
Simulation Set-Up and Results	p. 53
Analysis and Test of URRF and URWF	p. 54
Functional Fault Modeling of URRF and URWF	p. 54
Experiments	p. 55
March Test Solutions Detecting URWFs	p. 60
Conclusion	p. 64
Resistive-Open Defects in Address Decoders	p. 65
The SRAM Address Decoder	p. 65
Analysis of Resistive-Open Defects in the Address Decoder	p. 67
Analysis and Test of ADOF	p. 67
Functional Fault Modeling of ADOF	p. 68
Experiments	p. 70
March Test Solution Detecting ADOFs	p. 75
Conclusion	p. 80
Resistive-Open Defects in Write Drivers	p. 81
The SRAM Write Driver	p. 81
Write Driver Within the I/O Circuitry	p. 81
Operation Mode of the Write Driver	p. 82
Analysis of Resistive-Open Defects in the Write Driver	p. 84
Defect Location	p. 84
Defect Incidence Analysis	p. 85
Simulation Set-Up and Results	p. 86
Analysis and Test of SWDF	p. 87
Functional Fault Modeling of SWDF	p. 87
Experiments	p. 88
March Test Solution Detecting SWDFs	p. 90
Analysis and Test of URWF/URDWF	p. 92
Functional Fault Modeling of URDWF	p. 92
Experiments	p. 93
March Test Solution Detecting URDWFs	p. 96
Conclusion	p. 96
Resistive-Open Defects in Sense Amplifiers	p. 99
The SRAM Sense Amplifier	p. 99
Sense Amplifier Within the I/O Circuitry	p. 99
Operation Mode of the Sense Amplifier	p. 99
Analysis of Resistive-Open Defects in the Sense Amplifier	p. 102
Defect Location	p. 103
Defect Incidence Analysis	p. 103
Simulation Set-Up and Results	p. 104
Analysis and Test of d2cIRF1	p. 105
Functional Fault Modeling of d2cIRF1	p. 105
Experiments	p. 106
March Test Solution Detecting d2cIRF1s	p. 107
Analysis and Test of d2cIRF2	p. 110
Functional Fault Modeling of d2cIRF2	p. 110
Experiments	p. 111
March Test Solution Detecting d2cIRF2s	p. 112
d2cIRF1 vs. d2cIRF2	p. 113
Conclusion	p. 114
Faults Due to Process Variations in SRAMs	p. 115
Influence of Threshold Voltage Deviations in SRAM Core-Cells	p. 115
Simulation Flow	p. 116
Mismatch Sensitivity During Read/Write Operations	p. 116
V₁ Mismatch Related Fault Models	p. 119
Impact of Leakage Current of Core-Cell Pass-Transistors on the Read Operation	p. 122
Analysis of Supply Voltage Variations	p. 127
Analysis of Temperature Variations	p. 128
Test and Diagnosis of LRFs	p. 128
Complex Read Fault Analysis	p. 130
Conclusion	p. 132
Diagnosis and Design-for-Diagnosis	p. 133
Diagnosis Methods	p. 133
Cause-Effect Approach: Signature-Based Diagnosis	p. 133
Effect-Cause Approach: History-Based Diagnosis	p. 137
Design-for-Diagnosis of Write Drivers	p. 150
Requirements for Fault-Free Operations of a Write Driver	p. 150
Description of the Current-Based DfD Solution	p. 152
Description of the Voltage-Based DfD Solution	p. 154
Diagnosis Sequence	p. 157
Conclusion	p. 158
Summary	p. 159
References	p. 163
Index	p. 169
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Advanced Test Methods for SRAMs

Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

At a Glance

Hardcover

Shipping

How to return your order

Defective items

You Can Find This Book In

Other Editions and Formats

Paperback

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