Advances in Computer Systems Architecture

9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings

By: Pen-Chung Yew (Editor), Jingling Xue (Editor)

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Paperback | 14 September 2004

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On behalf of the program committee, we were pleased to present this year's program for ACSAC: Asia-Paci?c Computer Systems Architecture Conference. Now in its ninth year, ACSAC continues to provide an excellent forum for researchers, educators and practitioners to come to the Asia-Paci?c region to exchange ideas on the latest developments in computer systems architecture. This year, the paper submission and review processes were semiautomated using the free version of CyberChair. We received 152 submissions, the largest number ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ?ve committee members for review. All of the papers were reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the review process. When reviewers claimed inadequate expertise, additional reviewers were solicited. In the end, we received a total of 594 reviews (3.9 per paper) from committee members as well as 248 coreviewers whose names are acknowledged in the proceedings. We would like to thank all of them for their time and e?ort in providing us with such timely and high-quality reviews, some of them on extremely short notice.

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Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Mathematics Operating Systems Computer Networking & Communications EDI Electronic Data Interchange Computer Hardware Network Hardware Systems Analysis & Design

Some real observations on virtual machines	p. 1
Replica victim caching to improve reliability of in-cache replication	p. 2
Efficient victim mechanism on sector cache organization	p. 16
Cache behavior analysis of a compiler-assisted cache replacement policy	p. 30
Modeling the cache behavior of codes with arbitrary data-dependent conditional structures	p. 44
A configurable system-on-chip architecture for embedded devices	p. 58
An auto-adaptative reconfigurable architecture for the control	p. 72
Enhancing the memory performance of embedded systems with the flexible sequential and random access memory	p. 88
Heuristic algorithm for reducing mapping sets of hardware-software partitioning in reconfigurable system	p. 102
Architecture design of a high-performance 32-bit fixed-point DSP	p. 115
TengYue-1 : a high performance embedded SoC	p. 126
A fault-tolerant single-chip multiprocessor	p. 137
Initial experiences with dreamy memory and the RAMpage memory hierarchy	p. 146
dDVS : an efficient dynamic voltage scaling algorithm based on the differential of CPU utilization	p. 160
High performance microprocessor design methods exploiting information locality and data redundancy for lower area cost and power consumption	p. 170
Dynamic reallocation of functional units in superscalar processors	p. 185
Multiple-dimension scalable adaptive stream architecture	p. 199
Impact of register-cache bandwidth variation on processor performance	p. 212
Exploiting free execution slots on EPIC processors for efficient and accurate runtime profiling	p. 226
Continuous adaptive object-code re-optimization framework	p. 241
Initial evaluation of a user-level device driver framework	p. 256
A generation ahead of microprocessor : where software can drive uArchitecture to?	p. 270
A cost-effective supersampling for full scene AntiAliasing	p. 271
A simple architectural enhancement for fast and flexible elliptic curve cryptography over binary finite fields GF(2[superscript m])	p. 282
Scalable design framework for JPEG2000 system architecture	p. 296
Real-time three dimensional vision	p. 309
A router architecture for QoS capable clusters	p. 321
Optimal scheduling algorithms in WDM optical interconnects with limited range wavelength conversion capability	p. 335
Comparative evaluation of adaptive and deterministic routing in the OTIS-hypercube	p. 349
A two-level on-chip bus system based on multiplexers	p. 363
Make computers cheaper and simpler	p. 373
A low power branch predictor to selectively access the BTB	p. 374
Static techniques to improve power efficiency of branch predictors	p. 385
Choice predictor for free	p. 399
Performance impact of different data value predictors	p. 414
Heterogeneous networks of workstations	p. 426
Finding high performance solution in reconfigurable mesh-connected VLSI arrays	p. 440
Order independent transparency for image composition parallel rendering machines	p. 449
An authorization architecture oriented to engineering and scientific computation in grid environments	p. 461
Validating word-oriented processors for bit and multi-word operations	p. 473
Dynamic fetch engine for simultaneous multithreaded processors	p. 489
A novel rename register architecture and performance analysis	p. 503
A new hierarchy cache scheme using RAM and Pagefile	p. 515
An object-oriented data storage system on network-attached object devices	p. 527
A scalable and adaptive directory scheme for hardware distributed shared memory	p. 539
A compiler-assisted on-chip assigned-signature control flow checking	p. 554
A floating point divider performing IEEE rounding and quotient conversion in parallel	p. 568
Efficient buffer allocation for asynchronous linear pipelines by design space localization	p. 582
Table of Contents provided by Blackwell. All Rights Reserved.

Advances in Computer Systems Architecture

9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings

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