ASIC and FPGA Verification

A Guide to Component Modeling

By: Richard Munden

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Paperback | 1 September 2004

At a Glance

Paperback
336 Pages

Dimensions(cm)
23.5 x 19.05 x 2.54

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$193.99

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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.

Industry Reviews

Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possible-the availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible. -Randy Harr, Sevni Technology This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation. -Hardy Pottinger, University of Missouri-Rolla

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Computer Programming & Software Development Software Engineering Computer Science Computer Architecture & Logic Design Graphical & Digital Media Applications 3D Graphics & Modelling

Electronic Devices & Materials

Introduction to Board-Level Verification
Tour of a simple model
VHDL packages for component models
Introduction to SDF
Anatomy of a VITAL Model
Modeling Delays
VITAL truth tables
Modeling timing constraints
Modeling registered devices
Conditional delays and timing constraints
Negative timing constraints
Timing Files and Backannotation
Adding Timing to Your RTL Code
Modeling Memories
Considerations for Component Modeling
Modeling Component Centric Features
Testbenches for Component Models
Table of Contents provided by Publisher. All Rights Reserved.

ASIC and FPGA Verification

A Guide to Component Modeling

At a Glance

Paperback

Industry Reviews

Shipping

How to return your order

Defective items

You Can Find This Book In

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