Automated Technology for Verification and Analysis

Third International Symposium, ATVA 2005, Taipei, Taiwan, October 4-7, 2005, Proceedings

By: Doron A. Peled (Editor), Yih-Kuen Tsay (Editor)

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Paperback | 19 September 2005

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The Automated Technology for Veri?cation and Analysis (ATVA) international symposium series was initiated in 2003, responding to a growing interest in formal veri?cation spurred by the booming IT industry, particularly hardware design and manufacturing in East Asia. Its purpose is to promote research on automated veri?cation and analysis in the region by providing a forum for int- action between the regional and the international research/industrial commu- ties of the ?eld. ATVA 2005, the third of the ATVA series, was held in Taipei, Taiwan, October 4-7, 2005. The main theme of the symposium encompasses - sign, complexities, tools, and applications of automated methods for veri?cation and analysis. The symposium was co-located and had a two-day overlap with FORTE 2005, which was held October 2-5, 2005. We received a total of 95 submissions from 17 countries. Each submission was assigned to three Program Committee members, who were helped by their subreviewers, for rigorous and fair evaluation. The ?nal deliberation by the P- gram Committee was conducted over email for a duration of about 10 days after nearly all review reports had been collected. In the end, 33 papers were - lectedforinclusionintheprogram.ATVA2005hadthreekeynotespeechesgiven respectively by Amir Pnueli (joint with FORTE 2005), Zohar Manna, and Wo- gang Thomas. The main symposium was preceded by a tutorial day, consisting of three two-hour lectures given also by the keynote speakers.

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You Can Find This Book In

Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Computer Networking & Communications Systems Analysis & Design Graphical & Digital Media Applications Computer-Aided Design CAD Computer Programming & Software Development Programming & Scripting Languages Digital Lifestyle & Online World: Consumer & User Guides Internet Guides & Online Services

Artificial Intelligence Expert Systems & Knowledge-Based Systems Computer Hardware Network Hardware

Ranking abstraction as a companion to predicate abstraction	p. 1
Termination and invariance analysis of loops	p. 2
Some perspectives of infinite-state verification	p. 3
Verifying very large industrial circuits using 100 processes and beyond	p. 11
A new reachability algorithm for symmetric multi-processor architecture	p. 26
Comprehensive verification framework for dependability of self-optimizing systems	p. 39
Exploiting hub states in automatic verification	p. 54
An approach for the verification of SystemC designs using AsmL	p. 69
Decomposition-based verification of cyclic workflows	p. 84
Guaranteed termination in the verification of LTL properties of non-linear robust discrete time hybrid systems	p. 99
Computation platform for automatic analysis of embedded software systems using model based approach	p. 114
Quantitative and qualitative analysis of temporal aspects of complex activities	p. 129
Automatic test case generation with region-related coverage annotations for real-time systems	p. 144
Selective search in bounded model checking of reachability properties	p. 159
Predicate abstraction of RTL verilog descriptions using constraint logic programming	p. 174
State space exploration of object-based systems using equivalence reduction and the sweepline method	p. 187
Syntactical colored petri nets reductions	p. 202
Algorithmic algebraic model checking II : decidability of semi-algebraic model checking and its applications to systems biology	p. 217
A static analysis using tree automata for XML access control	p. 234
Reasoning about transfinite sequences	p. 248
Semi-automatic distributed synthesis	p. 263
A new graph of classes for the preservation of quantitative temporal constraints	p. 278
Comparison of different semantics for time petri nets	p. 293
Introducing dynamic properties with past temporal operators in the B refinement	p. 308
Approximate reachability for dead code elimination in esterel*	p. 323
Synthesis of interface automata	p. 338
Multi-valued model checking games	p. 354
Model checking prioritized timed automata	p. 370
An MTBDD-based implementation of forward reachability for probabilistic timed automata	p. 385
An EFSM-based intrusion detection system for ad hoc networks	p. 400
Modeling and verification of a telecommunication application using live sequence charts and the play-engine tool	p. 414
Formal construction and verification of home service robots : a case study	p. 429
Model checking real time Java using Java PathFinder	p. 444
Using parametric automata for the verification of the stop-and-wait class of protocols	p. 457
Flat acceleration in symbolic model checking	p. 474
Flat counter automata almost everywhere!	p. 489
Table of Contents provided by Blackwell. All Rights Reserved.

Automated Technology for Verification and Analysis

Third International Symposium, ATVA 2005, Taipei, Taiwan, October 4-7, 2005, Proceedings

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