Automated Technology for Verification and Analysis

Second International Conference, Atva 2004, Taipei, Taiwan, Roc, October 31 - November 3, 2004, Proceedings

By: Farn Wang (Editor)

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Paperback | 1 November 2004

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It was our great pleasure to hold the 2nd International Symposium onAutomated Te- nology on Veri?cation and Analysis (ATVA) in Taipei, Taiwan, ROC, October 31- November3,2004.TheseriesofATVAmeetingsisintendedforthepromotionofrelated research in eastern Asia. In the last decade, automated technology on veri?cation has become the new strength in industry and brought forward various hot research activities in both Europe and USA. In comparison, easternAsia has been quiet in the forum.With more and more IC design houses moving from SiliconValley to easternAsia, we believe this is a good time to start cultivating related research activities in the region. TheemphasisoftheATVAworkshopseriesisonvariousmechanicalandinformative techniques, which can give engineers valuable feedback to fast converge their designs according to the speci?cations. The scope of interest contains the following research - eas: model-checking theory, theorem-proving theory, state-space reduction techniques, languages in automated veri?cation, parametric analysis, optimization, formal perf- mance analysis, real-time systems, embedded systems, in?nite-state systems, Petri nets, UML, synthesis, tools, and practice in industry.

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Keynote Speech
Games for Formal Design and Verification of Reactive Systems	p. 1
Evolution of Model Checking into the EDA Industry	p. 2
Abstraction Refinement	p. 7
Invited Speech
Tools for Automated Verification of Web Services	p. 8
Theorem Proving Languages for Verification	p. 11
An Automated Rigorous Review Method for Verifying and Validating Formal Specifications	p. 15
Papers
Toward Unbounded Model Checking for Region Automata	p. 20
Search Space Partition and Case Basis Exploration for Reducing Model Checking Complexity	p. 34
Synthesising Attacks on Cryptographic Protocols	p. 49
Büchi Complementation Made Tighter	p. 64
SAT-Based Verification of Safe Petri Nets	p. 79
Disjunctive Invariants for Numerical Systems	p. 93
Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas	p. 108
Fair Testing Revisited: A Process-Algebraic Characterisation of Conflicts	p. 120
Exploiting Symmetries for Testing Equivalence in the Spi Calculus	p. 135
Using Block-Local Atomicity to Detect Stale-Value Concurrency Errors	p. 150
Abstraction-Based Model Checking Using Heuristical Refinement	p. 165
A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata	p. 179
Design and Evaluation of a Symbolic and Abstraction-Based Model Checker	p. 196
Component-Wise Instruction-Cache Behavior Prediction	p. 211
Validating the Translation of an Industrial Optimizing Compiler	p. 230
Composition of Accelerations to Verify Infinite Heterogeneous Systems	p. 248
Hybrid System Verification Is Not a Sinecure (The Electronic Throttle Control Case Study)	p. 263
Providing Automated Verification in HOL Using MDGs	p. 278
Specification, Abduction, and Proof	p. 294
Introducing Structural Dynamic Changes in Petri Nets: Marked-Controlled Reconfigurable Nets	p. 310
Typeness for -Regular Automata	p. 324
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits	p. 339
Mutation Coverage Estimation for Model Checking	p. 354
Modular Model Checking of Software Specifications with Simultaneous Environment Generation	p. 369
Rabin Tree and Its Application to Group Key Distribution	p. 384
Using Overlay Networks to Improve VoIP Reliability	p. 392
Integrity-Enhanced Verification Scheme for Software-Intensive Organizations	p. 402
RCGES: Retargetable Code Generation for Embedded Systems	p. 415
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets	p. 426
First-Order LTL Model Checking Using MDGs	p. 441
Localizing Errors in Counter example with Iteratively Witness Searching	p. 456
Verification of WCDMA Protocols and Implementation	p. 470
Efficient Representation of Algebraic Expressions	p. 474
Development of RTOS for PLC Using Formal Methods	p. 479
Reducing Parametric Automata: A Multimedia Protocol Service Case Study	p. 483
Synthesis of State Feedback Controllers for Parameterized Discrete Event Systems	p. 487
Solving Box-Pushing Games via Model Checking with Optimizations	p. 491
CLP Based Static Property Checking	p. 495
A Temporal Assertion Extension to Verilog	p. 499
Author Index	p. 505
Table of Contents provided by Publisher. All Rights Reserved.

Automated Technology for Verification and Analysis

Second International Conference, Atva 2004, Taipei, Taiwan, Roc, October 31 - November 3, 2004, Proceedings

At a Glance

Paperback

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