CMOS Memory Circuits

By: Tegze P. Haraszti

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Hardcover | 30 September 2000

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Hardcover
580 Pages

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24.13 x 15.88 x 3.18

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CMOS Memory Circuits is a systematic and comprehensive reference work designed to aid in the understanding of CMOS memory circuits, architectures, and design techniques.
CMOS technology is the dominant fabrication method and almost the exclusive choice for semiconductor memory designers.
Both the quantity and the variety of complementary-metal-oxide-semiconductor (CMOS) memories are staggering. CMOS memories are traded as mass-products worldwide and are diversified to satisfy nearly all practical requirements in operational speed, power, size, and environmental tolerance. Without the outstanding speed, power, and packing density characteristics of CMOS memories, neither personal computing, nor space exploration, nor superior defense systems, nor many other feats of human ingenuity could be accomplished. Electronic systems need continuous improvements in speed performance, power consumption, packing density, size, weight, and costs. These needs continue to spur the rapid advancement of CMOS memory processing and circuit technologies.
CMOS Memory Circuits is essential for those who intend to (1) understand, (2) apply, (3) design and (4) develop CMOS memories.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Electronic Devices & Materials Semi-Conductors & Super-Conductors Computing & I.T.Computer Hardware Storage Media & Peripherals Energy Technology & Engineering Electrical Engineering

Computer Science Systems Analysis & Design

Preface	p. xi
Conventions	p. xvi
Introduction to CMOS Memories	p. 1
Classification and Characterization of CMOS Memories	p. 2
Random Access Memories	p. 10
Fundamentals	p. 10
Dynamic Random Access Memories (DRAMs)	p. 11
Pipelining in Extended Data Output (EDO) and Burst EDO (BEDO) DRAMs	p. 20
Synchronous DRAMs (SDRAMs)	p. 25
Wide DRAMs	p. 31
Video DRAMs	p. 33
Static Random Access Memories (SRAMs)	p. 36
Pseudo SRAMs	p. 40
Read Only Memories (ROMs)	p. 41
Sequential Access Memories (SAMs)	p. 42
Principles	p. 42
RAM-Based SAMs	p. 44
Shift-Register Based SAMs	p. 45
Shuffle Memories	p. 48
First-In-First-Out Memories (FIFOs)	p. 51
Content Addressable Memories (CAMs)	p. 54
Basics	p. 54
All-Parallel CAMs	p. 56
Word-Serial-Bit-Parallel CAMs	p. 58
Word-Parallel-Bit-Serial CAMs	p. 59
Special Memories and Combinations	p. 61
Cache-Memory Fundamentals	p. 61
Basic Cache Organizations	p. 65
DRAM-Cache Combinations	p. 70
Enhanced DRAM (EDRAM)	p. 70
Cached DRAM (CDRAM)	p. 72
Rambus DRAM (RDRAM)	p. 73
Virtual Channel Memory (VCM)	p. 76
Nonranked and Hierarchical Memory Organizations	p. 80
Memory Cells	p. 85
Basics, Classifications and Objectives	p. 86
Dynamic One-Transistor-One-Capacitor Random Access Memory Cell	p. 89
Dynamic Storage and Refresh	p. 89
Write and Read Signals	p. 92
Design Objectives and Trade-offs	p. 96
Implementation Issues	p. 97
Insulator Thickness	p. 97
Insulator Material	p. 98
Parasitic Capacitances	p. 103
Effective Capacitor Area	p. 105
Dynamic Three-Transistor Random Access Memory Cell	p. 110
Description	p. 110
Brief Analysis	p. 111
Static 6-Transistor Random Access Memory Cell	p. 113
Static Full-Complementary Storage	p. 113
Write and Read Analysis	p. 116
Design Objectives and Concerns	p. 121
Implementations	p. 122
Static Four-Transistor-Two-Resistor Random Access Memory Cells	p. 125
Static Noncomplementary Storage	p. 125
Design and Implementation	p. 128
Read-Only Memory Cells	p. 132
Read-Only Storage	p. 132
Programming and Design	p. 134
Shift-Register Cells	p. 136
Data Shifting	p. 136
Dynamic Shift-Register Cells	p. 138
Static Shift-Register Cells	p. 143
Content Addressable Memory Cells	p. 146
Associative Access	p. 146
Circuit Implementations	p. 148
Other Memory Cells	p. 151
Considerations for Uses	p. 151
Tunnel-Diode Based Memory Cells	p. 152
Charge Coupled Device	p. 154
Multiport Memory Cells	p. 156
Derivative Memory Cells	p. 158
Sense Amplifiers	p. 163
Sense Circuits	p. 164
Data Sensing	p. 164
Operation Margins	p. 166
Terms Determining Operation Margins	p. 171
Supply Voltage	p. 171
Threshold Voltage Drop	p. 171
Leakage Currents	p. 173
Charge-Couplings	p. 176
Imbalances	p. 179
Other Specific Effects	p. 181
Precharge Level Variations	p. 182
Sense Amplifiers in General	p. 184
Basics	p. 184
Designing Sense Amplifiers	p. 187
Classification	p. 190
Differential Voltage Sense Amplifiers	p. 192
Basic Differential Voltage Amplifier	p. 192
Description and Operation	p. 192
DC Analysis	p. 193
AC Analysis	p. 196
Simple Differential Voltage Sense Amplifier	p. 200
All-Transistor Sense Amplifier Circuit	p. 200
AC Analysis	p. 201
Transient Analysis	p. 203
Full-Complementary Differential Voltage Sense Amplifier	p. 207
Active Load Application	p. 207
Analysis and Design Considerations	p. 209
Positive Feedback Differential Voltage Sense Amplifier	p. 211
Circuit Operation	p. 211
Feedback Analysis	p. 213
Full-Complementary Positive-Feedback Differential Voltage Sense Amplifier	p. 217
Enhancements to Differential Voltage Sense Amplifiers	p. 220
Approaches	p. 220
Decoupling Bitline Loads	p. 221
Feedback Separation	p. 224
Current Sources	p. 226
Optimum Voltage-Swing to Sense Amplifiers	p. 229
Current Sense Amplifiers	p. 232
Reasons for Current Sensing	p. 232
Feedback Types and Impedances	p. 236
Current-Mirror Sense Amplifier	p. 238
Positive Feedback Current Sense Amplifier	p. 240
Positive Feedback Current Sense Amplifier	p. 240
Current-Voltage Sense Amplifier	p. 243
Crosscoupled Positive Feedback Current Sense Amplifier	p. 245
Negative Feedback Current Sense Amplifiers	p. 249
Feedback Transfer Functions	p. 250
Improvements by Feedback	p. 252
Stability and Transient Damping	p. 256
Offset Reduction	p. 257
Offsets in Sense Amplifiers	p. 257
Offset Reducing Layout Designs	p. 259
Negative Feedback for Offset Decrease	p. 260
Sample-and-Feedback Offset Limitation	p. 263
Nondifferential Sense Amplifiers	p. 265
Basics	p. 265
Common-Source Sense Amplifiers	p. 266
Common-Gate Sense Amplifiers	p. 269
Common-Drain Sense Amplifiers	p. 273
Memory Constituent Subcircuits	p. 277
Array Wiring	p. 278
Bitlines	p. 278
Simple Models	p. 278
Signal Limiters	p. 283
Wordlines	p. 287
Modelling	p. 287
Signal Control	p. 290
Transmission Line Models	p. 296
Signal Propagation and Reflections	p. 296
Signal Transients	p. 301
Validity Regions of Transmission Line Models	p. 308
Reference Circuits	p. 311
Basic Functions	p. 311
Voltage References	p. 311
Current References	p. 318
Charge References	p. 321
Decoders	p. 323
Output Buffers	p. 328
Input Receivers	p. 336
Clock Circuits	p. 341
Operation Timing	p. 341
Clock Generators	p. 344
Clock Recovery	p. 347
Clock Delay and Transient Control	p. 352
Power-Lines	p. 355
Power Distribution	p. 355
Power-Line Bounce Reduction	p. 359
Reliability and Yield Improvement	p. 365
Reliability and Redundancy	p. 366
Memory Reliability	p. 366
Redundancy Effects on Reliability	p. 369
Noises in Memory Circuits	p. 373
Noises and Noise Sources	p. 373
Crosstalk Noises in Arrays	p. 374
Crosstalk Reduction in Bitlines	p. 379
Power-Line Noises in Arrays	p. 382
Thermal Noise	p. 385
Charged Atomic Particle Impacts	p. 388
Effects of Charged Atomic Particle Impacts	p. 388
Error Rate Estimate	p. 390
Error Rate Reduction	p. 398
Yield and Redundancy	p. 402
Memory Yield	p. 402
Yield Improvement by Redundancy Applications	p. 406
Fault-Tolerance in Memory Designs	p. 412
Faults, Failures, Errors and Fault-Tolerance	p. 412
Faults and Errors to Repair and Correct	p. 415
Strategies for Fault-Tolerance	p. 420
Fault Repair	p. 421
Fault Repair Principles in Memories	p. 421
Programming Elements	p. 423
Row and Column Replacement	p. 428
Associative Repair	p. 434
Fault Masking	p. 436
Error Control Code Application in Memories	p. 438
Coding Fundamentals	p. 438
Code Performance	p. 442
Code Efficiency	p. 446
Linear Systematic Codes	p. 453
Description	p. 453
Single Parity Check Code	p. 453
Berger Codes	p. 455
BCH Codes	p. 457
Binary Hamming Codes	p. 457
Reed-Solomon (RS) Codes	p. 461
Bidirectional Codes	p. 462
Combination of Error Control Coding and Fault-Repair	p. 464
Radiation Effects and Circuit Hardening	p. 469
Radiation Effects	p. 470
Radiation Environments	p. 470
Permanent Ionization Total-Dose Effects	p. 471
Transient Ionization Dose-Rate Effects	p. 475
Fabrication-Induced Radiations and Neutron Fluence	p. 477
Combined Radiation Effects	p. 478
Radiation Hardening	p. 481
Requirements and Hardening Methods	p. 481
Self-Compensation and Voltage Limitation in Sense Circuits	p. 486
Parameter Tracking in Reference Circuits	p. 491
State Retention in Memory Cells	p. 493
Self-Adjusting Logic Gates	p. 495
Global Fault-Tolerance for Radiation Hardening	p. 499
Designing Memories in CMOS SOI (SOS)	p. 501
Basic Considerations	p. 501
Devices	p. 501
Features	p. 505
Floating Substrate Effects	p. 509
History Dependency, Kinks and Passgate Leakages	p. 509
Relieves	p. 516
Side- and Back-Channel Effects	p. 520
Side-Channel Leakages, Kinks and Breakdowns	p. 520
Back-Channel- and Photocurrents	p. 524
Allays	p. 526
Diode-Like Nonlinear Parasitic Elements and Others	p. 527
References	p. 531
Index	p. 541
Table of Contents provided by Syndetics. All Rights Reserved.

CMOS Memory Circuits

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Hardcover

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