Correct Hardware Design and Verification Methods

IFIP WG10.5 Advanced Research Working Conference, CHARME '95, Frankfurt, Germany, October 1995. Proceedings

By: Paolo Enrico Camurati (Editor), Hans Eveking (Editor)

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Paperback | 18 September 1995

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This book constitutes the refereed proceedings of the IFIP WG10.5 Advanced Research Working Conference on Correct Hardware Design Methodologies, CHARME '95, held in Frankfurt, Germany, in October 1995.
The 20 revised full papers presented were carefully selected by the program committee and address all current aspects of research and advanced applications in the field of formal verification of hardware. Among the topics covered are model checking, theorem proving, formally verified synthesis, process algebras, finite state systems, verification environments, language containment, and VHDL.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Graphical & Digital Media Applications Computer-Aided Design CAD Computer Science Computer Architecture & Logic Design Energy Technology & Engineering Electrical Engineering

Systems Analysis & Design Computer Networking & Communications EDI Electronic Data Interchange Computer Programming & Software Development Software Engineering

What if model checking must be truly symbolic	p. 1
Automatic verification of the SCI cache coherence protocol	p. 21
Describing and verifying synchronous circuits with the Boyer-Moore theorem prover	p. 35
Problems encountered in the machine-assisted proof of hardware	p. 56
Formally embedding existing high level synthesis algorithms	p. 71
Formal design of a class of computers	p. 84
Symbolic analysis and verification of CPA descriptions	p. 103
A foundation for formal reuse of hardware	p. 124
State enumeration with abstract descriptions of state machines	p. 146
Transforming boolean relations by symbolic encoding	p. 161
Design error diagnosis in sequential circuits	p. 171
Timing analysis of asynchronous circuits using timed automata	p. 189
Improved probabilistic verification by hash compaction	p. 206
Formal support for the ELLA hardware description language	p. 225
Verifying hardware components within JACK	p. 246
Language containment of non-deterministic [omega]-automata	p. 261
A partial-order approach to the verification of concurrent systems: checking liveness properties	p. 278
Semantics of a verification-oriented subset of VHDL	p. 293
Reasoning about VHDL using operational and observational semantics	p. 311
A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking	p. 328
Table of Contents provided by Blackwell. All Rights Reserved.

Correct Hardware Design and Verification Methods

IFIP WG10.5 Advanced Research Working Conference, CHARME '95, Frankfurt, Germany, October 1995. Proceedings

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