Digital VLSI Design with Verilog

A Textbook from Silicon Valley Polytechnic Institute

By: John Michael Williams

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Hardcover | 8 July 2014 | Edition Number 2

At a Glance

Hardcover
572 Pages

Edition Type
Revised

Dimensions(cm)
24.3 x 16.6 x 2.7

Hardcover

$249.00

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This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics includes System Verilog and Verilog-AMS.

Industry Reviews

"As the title states, this is a textbook for a graduate course on digital design. ... the text is mostly oriented to the professor, providing a perfect tool to drive the course. The text is well structured by weeks and class sessions ... needed to cover most of the aspects involved in an introductory digital design course. ... I am sure that students using this book will learn enough to start working in any Silicon company." (Javier Castillo, Computing Reviews, March, 2015)

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