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EDA for IC Implementation, Circuit Design, and Process Technology : Electronic Design Automation for Integrated Circuits Hdbk - Grant Martin

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EDA for IC Implementation, Circuit Design, and Process Technology

By: Grant Martin (Editor), Luciano Lavagno (Editor), Louis Scheffer (Editor)

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Hardcover | 23 March 2006 | Edition Number 1

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Hardcover
616 Pages

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25.5 x 18.7 x 4.4

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Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The second volume, EDA for IC Implementation, Circuit Design, and Process Technology, thoroughly examines real-time logic to GDSII (a file format used to transfer data of semiconductor physical layout), analog/mixed signal design, physical verification, and technology CAD (TCAD). Chapters contributed by leading experts authoritatively discuss design for manufacturability at the nanoscale, power supply network design and analysis, design modeling, and much more. Save on the complete set.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Electronic Devices & Materials Microprocessors Energy Technology & Engineering Electrical Engineering Environmental Science

RTL to GDS-II, or Synthesis, Place, and Route
Design Flows	p. 1-1
Introduction	p. 1-1
Invention	p. 1-2
Implementation	p. 1-2
Integration	p. 1-5
Future Scaling Challenges	p. 1-10
Conclusion	p. 1-12
Logic Synthesis	p. 2-1
Introduction	p. 2-1
Behavioral and Register Transfer-Level Synthesis	p. 2-2
Two-Level Minimization	p. 2-3
Multilevel Logic Minimization	p. 2-4
Enabling Technologies for Logic Synthesis	p. 2-10
Sequential Optimization	p. 2-11
Physical Synthesis	p. 2-13
Multivalued Logic Synthesis	p. 2-14
Summary	p. 2-15
Power Analysis and Optimization from Circuit to Register-Transfer Levels	p. 3-1
Introduction	p. 3-1
Power Analysis	p. 3-2
Circuit-Level Power Optimization	p. 3-8
Logic Synthesis for Low Power	p. 3-12
Conclusion	p. 3-15
Equivalence Checking	p. 4-1
Introduction	p. 4-1
Equivalence Checking Problem	p. 4-3
Boolean Reasoning	p. 4-5
Combinational Equivalence Checking	p. 4-10
Sequential Equivalence Checking	p. 4-14
Summary	p. 4-17
Digital Layout - Placement	p. 5-1
Introduction: Placement Problem and Contexts	p. 5-1
Global Placement	p. 5-4
Detailed Placement and Legalizers	p. 5-15
Placement Trends	p. 5-17
Academic and Industrial Placers	p. 5-19
Conclusions	p. 5-20
Static Timing Analysis	p. 6-1
Introduction	p. 6-1
Representation of Combinational and Sequential Circuits	p. 6-1
Gate Delay Models	p. 6-3
Timing Analysis for Combinational Circuits	p. 6-3
Timing Analysis for Sequential Circuits	p. 6-7
Clocking Disciplines: Edge-Triggered Circuits	p. 6-8
Clocking and Clock-Skew Optimization	p. 6-9
Statistical Static Timing Analysis	p. 6-12
Conclusion	p. 6-15
Structured Digital Design	p. 7-1
Introduction	p. 7-1
Datapaths	p. 7-2
Programmable Logic Arrays	p. 7-13
Memory and Register Files	p. 7-15
Structured Chip Design	p. 7-17
Summary	p. 7-21
Routing	p. 8-1
Introduction	p. 8-2
Types of Routers	p. 8-2
A Brief History of Routing	p. 8-4
Common Routing Algorithms	p. 8-5
Additional Router Considerations	p. 8-9
Exploring Challenges of Libraries for Electronic Design	p. 9-1
Introduction	p. 9-1
What Does It Mean to Design Libraries?	p. 9-1
How Did We Get Here, Anyway?	p. 9-2
Commercial Efforts	p. 9-5
What Makes the Effort Easier?	p. 9-5
The Enemies of Progress	p. 9-6
Environments That Drive Progress	p. 9-6
Libraries and What They Contain	p. 9-6
Summary	p. 9-7
Design Closure	p. 10-1
Introduction	p. 10-1
Current Practice	p. 10-13
The Future of Design Closure	p. 10-28
Conclusion	p. 10-30
Tools for Chip-Package Codesign	p. 11-1
Introduction	p. 11-1
Drivers for Chip-Package Codesign	p. 11-1
Digital System Codesign Issues	p. 11-2
Mixed-Signal Codesign Issues	p. 11-5
I/O Buffer Interface Standard and Other Macromodels	p. 11-5
Conclusions	p. 11-7
Design Databases	p. 12-1
Introduction	p. 12-1
History	p. 12-2
Modern Database Examples	p. 12-3
Fundamental Features	p. 12-4
Advanced Features	p. 12-9
Technology Data	p. 12-12
Library Data and Structures: Design-Data Management	p. 12-13
Interoperability Models	p. 12-13
FPGA Synthesis and Physical Design	p. 13-1
Introduction	p. 13-1
System-Level Tools	p. 13-6
Logic Synthesis	p. 13-6
Physical Design	p. 13-13
Looking Forward	p. 13-26
Analog and Mixed-Signal Design
Simulation of Analog and RF Circuits and Systems	p. 14-1
Introduction	p. 14-1
Differential-Algebraic Equations for Circuits via Modified Nodal Analysis	p. 14-2
Device Models	p. 14-4
Basic Circuit Simulation: DC Analysis	p. 14-10
Steady-State Analysis	p. 14-13
Multitime Analysis	p. 14-17
Noise in RF Design	p. 14-25
Conclusions	p. 14-35
Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits	p. 15-1
Introduction	p. 15-2
Top-Down Mixed-Signal Design Methodology	p. 15-2
Mixed-Signal and Behavioral Simulation	p. 15-8
Analog Behavioral and Power Model Generation Techniques	p. 15-14
Symbolic Analysis of Analog Circuits	p. 15-18
Conclusions	p. 15-20
Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A Survey	p. 16-1
Introduction	p. 16-1
Analog Layout Problems and Approaches	p. 16-2
Analog Cell Layout Strategies	p. 16-5
Mixed-Signal System Layout	p. 16-8
Field-Programmable Analog Arrays	p. 16-11
Conclusions	p. 16-11
Physical Verification
Design Rule Checking	p. 17-1
Introduction	p. 17-1
Geometric Algorithms for Physical Verification	p. 17-6
Hierarchical Data Structures	p. 17-7
Time Complexity of Hierarchical Analysis	p. 17-8
Connectivity Models	p. 17-9
Parallel Computing	p. 17-11
Future Roles for Verification	p. 17-11
Resolution Enhancement Techniques and Mask Data Preparation	p. 18-1
Introduction	p. 18-1
Lithographic Effects	p. 18-2
RET for Smaller k[subscript 1]	p. 18-5
Software Implementations of RET Solutions	p. 18-11
Mask Data Preparation	p. 18-24
Summary	p. 18-27
Design for Manufacturability in the Nanometer Era	p. 19-1
Introduction	p. 19-1
Taxonomy of Yield Loss Mechanisms	p. 19-3
Logic Design for Manufacturing	p. 19-6
Parametric Design for Manufacturing Methodologies	p. 19-13
Design for Manufacturing Integration in the Design Flow: Yield-Aware Physical Synthesis	p. 19-18
Summary	p. 19-20
Design and Analysis of Power Supply Networks	p. 20-1
Introduction	p. 20-1
Voltage-Drop Analysis Modes	p. 20-3
Linear System Solution Techniques	p. 20-5
Models for Power Distribution Networks	p. 20-8
Conclusions	p. 20-13
Noise Considerations in Digital ICs	p. 21-1
Introduction	p. 21-1
Why Has Noise Become a Problem for Digital Chips?	p. 21-2
Noise Effects in Digital Designs	p. 21-3
Static Noise Analysis	p. 21-7
Electrical Analysis	p. 21-14
Fixing Noise Problems	p. 21-18
Summary and Conclusions	p. 21-20
Layout Extraction	p. 22-1
Introduction	p. 22-1
Early History	p. 22-2
Problem Analysis	p. 22-2
System Capabilities	p. 22-3
Converting Drawn Geometries to Actual Geometries	p. 22-4
Designed Device Extraction	p. 22-5
Connectivity Extraction	p. 22-7
Parasitic Resistance Extraction	p. 22-8
Capacitance Extraction Techniques	p. 22-10
Inductance Extraction Techniques	p. 22-13
Network Reduction	p. 22-17
Process Variation	p. 22-18
Conclusions and Future Study	p. 22-19
Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation	p. 23-1
Introduction	p. 23-2
Mechanisms and Effects of Mixed-Signal Noise Coupling	p. 23-2
Modeling of Mixed-Signal Noise Coupling	p. 23-7
Mixed-Signal Noise Measurement and Validation	p. 23-18
Application to Placement and Power Distribution Synthesis	p. 23-19
Summary	p. 23-21
Technology CAD
Process Simulation	p. 24-1
Introduction	p. 24-1
Process Simulation Methods	p. 24-2
Ion Implantation	p. 24-3
Diffusion	p. 24-8
Oxidation	p. 24-12
Etch and Deposition	p. 24-13
Lithography and Photoresist Modeling	p. 24-20
Silicidation	p. 24-20
Mechanics Modeling	p. 24-20
Putting It All Together	p. 24-22
Conclusions	p. 24-23
Device Modeling-From Physics to Electrical Parameter Extraction	p. 25-1
Introduction	p. 25-1
MOS Technology and Intrinsic Device Modeling	p. 25-3
Parasitic Junction and Inhomogeneous Substrate Effects	p. 25-20
Device Technology Alternatives	p. 25-23
Conclusions	p. 25-26
High-Accuracy Parasitic Extraction	p. 26-1
Introduction	p. 26-2
Extraction via Fast Integral Equation Methods	p. 26-3
Introduction	p. 26-3
Forms of Maxwell's Equations	p. 26-3
Fast Field Solvers: Capacitance Solution	p. 26-5
Fast Inductance Solution	p. 26-7
Distributed RLC and Full Wave	p. 26-11
Conclusions	p. 26-14
Statistical Capacitance Extraction	p. 26-14
Introduction	p. 26-14
Theory	p. 26-15
Characteristics	p. 26-17
Summary	p. 26-22
Index	p. 1
Table of Contents provided by Ingram. All Rights Reserved.

EDA for IC Implementation, Circuit Design, and Process Technology

At a Glance

Hardcover

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