EDA for IC System Design, Verification, and Testing : Electronic Design Automation for Integrated Circuits Hdbk - Grant Martin

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EDA for IC System Design, Verification, and Testing

Name: EDA for IC System Design, Verification, and Testing
Brand: Taylor & Francis Inc
Price: 279.4 AUD
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By: Grant Martin (Editor), Luciano Lavagno (Editor), Louis Scheffer (Editor)

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Hardcover | 23 March 2006 | Edition Number 1

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Hardcover
544 Pages

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18.5 x 26.1 x 3.5

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Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The first volume, EDA for IC System Design, Verification, and Testing, thoroughly examines system-level design, microarchitectural design, logical verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for IC designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. Save on the complete set.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Electronic Devices & Materials Microprocessors Energy Technology & Engineering Electrical Engineering Environmental Science

Introduction
Overview	p. 1-1
Introduction to Electronic Design Automation for Integrated Circuits	p. 1-2
System Level Design	p. 1-6
Micro-Architecture Design	p. 1-8
Logical Verification	p. 1-8
Test	p. 1-9
RTL to GDS-II, or Synthesis, Place, and Route	p. 1-9
Analog and Mixed-Signal Design	p. 1-11
Physical Verification	p. 1-11
Technology Computer-Aided Design	p. 1-12
The Integrated Circuit Design Process and Electronic Design Automation	p. 2-1
Introduction	p. 2-1
Verification	p. 2-3
Implementation	p. 2-5
Design for Manufacturing	p. 2-11
System Level Design
Tools and Methodologies for System-Level Design	p. 3-1
Introduction	p. 3-1
Characteristics of Video Applications	p. 3-2
Other Application Domains	p. 3-3
Platform Characteristics	p. 3-3
Models of Computation and Tools for Model-Based Design	p. 3-6
Simulation	p. 3-13
Hardware/Software Cosynthesis	p. 3-14
Summary	p. 3-15
System-Level Specification and Modeling Languages	p. 4-1
Introduction	p. 4-1
A Survey of Domain-Specific Languages and Methods	p. 4-2
Heterogeneous Platforms and Methodologies	p. 4-12
Conclusions	p. 4-13
SoC Block-Based Design and IP Assembly	p. 5-1
The Economics of Reusable IP and Block-Based Design	p. 5-2
Standard Bus Interfaces	p. 5-3
Use of Assertion-Based Verification	p. 5-4
Use of IP Configurators and Generators	p. 5-5
The Design Assembly and Verification Challenge	p. 5-7
The SPIRIT XML Databook Initiative	p. 5-8
Conclusions	p. 5-10
Performance Evaluation Methods for Multiprocessor System-on-Chip Design	p. 6-1
Introduction	p. 6-1
Overview of Performance Evaluation in the Context of System Design Flow	p. 6-2
MPSoC Performance Evaluation	p. 6-9
Conclusion	p. 6-12
System-Level Power Management	p. 7-1
Introduction	p. 7-1
Dynamic Power Management	p. 7-2
Battery-Aware Dynamic Power Management	p. 7-10
Software-Level Dynamic Power Management	p. 7-13
Conclusions	p. 7-17
Processor Modeling and Design Tools	p. 8-1
Introduction	p. 8-1
Processor Modeling Using ADLs	p. 8-2
ADL-Driven Methodologies	p. 8-11
Conclusions	p. 8-18
Embedded Software Modeling and Design	p. 9-1
Introduction	p. 9-1
Synchronous vs. Asynchronous Models	p. 9-13
Synchronous Models	p. 9-13
Asynchronous Models	p. 9-16
Research on Models for Embedded Software	p. 9-34
Conclusions	p. 9-40
Using Performance Metrics to Select Microprocessor Cores for IC Designs	p. 10-1
Introduction	p. 10-1
The ISS as Benchmarking Platform	p. 10-3
Ideal Versus Practical Processor Benchmarks	p. 10-4
Standard Benchmark Types	p. 10-4
Prehistoric Performance Ratings: MIPS, MOPS, and MFLOPS	p. 10-5
Classic Processor Benchmarks (The Stone Age)	p. 10-6
Modern Processor Performance Benchmarks	p. 10-13
Configurable Processors and the Future of Processor-Core Benchmarks	p. 10-22
Conclusion	p. 10-25
Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis	p. 11-1
Introduction	p. 11-2
Background and Survey of the State of the Art	p. 11-3
Parallelizing HLS	p. 11-11
The SPARK PHLS Framework	p. 11-15
Summary	p. 11-16
Micro-Architecture Design
Cycle-Accurate System-Level Modeling and Performance Evaluation	p. 12-1
Introduction	p. 12-1
System Modeling and Design Methodology	p. 12-3
Back-Annotation of System-Level Modeling Objects	p. 12-6
Automatic Extraction of Statistical Features	p. 12-10
Open System-Level Modeling Issues	p. 12-16
Micro-Architectural Power Estimation and Optimization	p. 13-1
Introduction	p. 13-1
Background	p. 13-2
Architectural Template	p. 13-4
Micro-Architectural Power Modeling and Estimation	p. 13-5
Micro-Architectural Power Optimization	p. 13-14
Conclusions	p. 13-29
Design Planning	p. 14-1
Introduction	p. 14-1
Floorplans	p. 14-3
Wireplans	p. 14-9
A Formal System For Trade-Offs	p. 14-17
Logical Verification
Design and Verification Languages	p. 15-1
Introduction	p. 15-1
History	p. 15-2
Design Languages	p. 15-3
Verification Languages	p. 15-16
Conclusions	p. 15-26
Digital Simulation	p. 16-1
Introduction	p. 16-1
Event- vs. Process-Oriented Simulation	p. 16-3
Logic Simulation Methods and Algorithms	p. 16-3
Impact of Languages on Logic Simulation	p. 16-11
Logic Simulation Techniques	p. 16-13
Impact of HVLs on Simulation	p. 16-16
Summary	p. 16-16
Using Transactional-Level Models in an SoC Design Flow	p. 17-1
Introduction	p. 17-1
Related Work	p. 17-2
Overview of the System-to-RTL Design Flow	p. 17-4
TLM - A Complementary View for the Design Flow	p. 17-6
TLM Modeling Application Programming Interface	p. 17-11
Example of a Multimedia Platform	p. 17-13
Design Flow Automation	p. 17-15
Conclusion	p. 17-17
Assertion-Based Verification	p. 18-1
Introduction	p. 18-1
History	p. 18-2
State of the Art	p. 18-8
Hardware Acceleration and Emulation	p. 19-1
Introduction	p. 19-1
Emulator Architecture Overview	p. 19-4
Design Modeling	p. 19-9
Debugging	p. 19-14
Use Models	p. 19-15
The Value of In-Circuit Emulation	p. 19-17
Considerations for Successful Emulation	p. 19-17
Summary	p. 19-20
Formal Property Verification	p. 20-1
Introduction	p. 20-1
Formal Property Verification Methods and Technologies	p. 20-4
Software Formal Verification	p. 20-8
Summary	p. 20-11
Test
Design-For-Test	p. 21-1
Introduction	p. 21-1
The Objectives of Design-For-Test for Microelectronics Products	p. 21-2
Overview of Chip-Level Design-For-Test Techniques	p. 21-5
Conclusion	p. 21-33
Automatic Test Pattern Generation	p. 22-1
Introduction	p. 22-1
Combinational ATPG	p. 22-2
Sequential ATPG	p. 22-7
ATPG and SAT	p. 22-13
Applications of ATPG	p. 22-20
High-Level ATPG	p. 22-25
Analog and Mixed Signal Test	p. 23-1
Introduction	p. 23-1
Analog Circuits and Analog Specifications	p. 23-2
Testability Analysis	p. 23-4
Fault Modeling and Test Specification	p. 23-5
Catastrophic Fault Modeling and Simulation	p. 23-6
Parametric Faults, Worst-Case Tolerance Analysis, and Test Generation	p. 23-6
Design for Test - An Overview	p. 23-7
Analog Test Bus Standard	p. 23-7
Oscillation-Based DFT/BIST	p. 23-8
PLL, VCO, and Jitter Testing	p. 23-10
Review of Jitter Measurement Techniques	p. 23-11
Summary	p. 23-22
Index	p. 1
Table of Contents provided by Ingram. All Rights Reserved.

EDA for IC System Design, Verification, and Testing

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Hardcover

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