Introduction | p. 1 |
A Definition of a Model | p. 1 |
A Day in the Life of a Model | p. 2 |
Types of Model | p. 7 |
Models of Computation | p. 8 |
Simplification | p. 10 |
Abstraction | p. 10 |
Structure | p. 10 |
Models and Languages | p. 12 |
Imperative Languages | p. 12 |
Declarative Languages | p. 13 |
Functional | p. 14 |
Non-functional | p. 15 |
Meta | p. 16 |
Testbench | p. 17 |
The Desire for a New Language | p. 18 |
Big Shoes to Fill | p. 19 |
Ptolemy Simulator | p. 20 |
SystemC | p. 21 |
Function and Interface | p. 22 |
Taxonomy | p. 22 |
Three New Axes | p. 23 |
Application to Models and Languages | p. 25 |
Transformation of Models | p. 27 |
Definitions | p. 28 |
References | p. 31 |
IP Meta-Models for SoC Assembly and HW/SW Interfaces | p. 33 |
Introduction | p. 33 |
IP Databases | p. 33 |
SPIRIT/IP-XACT | p. 34 |
History of SPIRIT | p. 34 |
RTL Assembly Level | p. 37 |
System Modeling Level | p. 41 |
Register Definition Languages | p. 41 |
Motivation: Modeling the HW/SW Interface | p. 42 |
HW/SW Design Flow for HW/SW Interfaces | p. 56 |
Emerging HW/SW Interface Tools and Design Flows | p. 74 |
Conclusions | p. 80 |
References | p. 81 |
Functional Models | p. 83 |
Dynamic Models and Languages | p. 84 |
Algorithmic Languages | p. 84 |
Architectural Modeling Languages: SystemC | p. 91 |
Architectural Models | p. 134 |
Formal Models | p. 137 |
Property Languages | p. 137 |
References | p. 141 |
Testbench Models | p. 143 |
Testbench Basics | p. 144 |
Testbench Components | p. 146 |
Verification Methodologies | p. 149 |
Verification IP | p. 152 |
Verification Plan | p. 152 |
Comparison Model | p. 157 |
Testbench Languages | p. 158 |
Progress Model | p. 161 |
Ad Hoc Metrics | p. 161 |
Structural Metrics | p. 161 |
Functional Metrics | p. 162 |
Coverage Metrics in SystemC | p. 162 |
Coverage Metrics in System Verilog | p. 165 |
Input Constraints | p. 166 |
Verification IP | p. 168 |
VIP Components | p. 169 |
VIP Standardization | p. 170 |
Conclusions | p. 171 |
References | p. 171 |
Virtual Prototypes and Mixed Abstraction Modeling | p. 173 |
Introduction | p. 175 |
Historical Perspective | p. 176 |
Use Models | p. 179 |
Technology | p. 183 |
Interfaces | p. 187 |
Processor Models | p. 188 |
System Prototypes | p. 191 |
Development Environments for Software Development | p. 191 |
Hybrid Hardware-Software-Based Development Platforms | p. 193 |
Hybrid System Prototyping Use Models | p. 194 |
Constructing a System-Level Virtual Prototype | p. 195 |
Modeling Languages | p. 196 |
Model Creation | p. 200 |
Model Import | p. 201 |
Model Libraries | p. 201 |
Virtual Devices | p. 202 |
Modeling the Environment | p. 204 |
Tying it all Together | p. 205 |
Documentation | p. 205 |
Running the Prototype | p. 206 |
Debug | p. 207 |
Analysis | p. 208 |
Verification | p. 214 |
Platform Deployment | p. 214 |
Verification Methodology Manual | p. 215 |
Building the RTL Testbench | p. 216 |
Regressions | p. 217 |
Example | p. 218 |
The Application | p. 219 |
The Bottom Line | p. 222 |
The Future | p. 223 |
References | p. 224 |
Processor-Centric Design: Processors, Multi-Processors, and Software | p. 225 |
Choices and Trade-Offs in Processor-Centric Design | p. 225 |
An ASIP Integrated Development Environment (IDE) | p. 229 |
Introduction to Flow and Example | p. 232 |
Starting with Algorithms | p. 234 |
Processor Definition | p. 234 |
Designing the Design Space Exploration | p. 234 |
Exploring the Processor Design Space: Preconfigured Cores | p. 234 |
Exploring the Processor Design Space: Automatically | p. 240 |
Exploring the Processor Design Space: Cache and Memory | p. 248 |
Exploring the Processor Design Space: Fine-Tuning | p. 249 |
Speed-Area-Power Trade-offs | p. 252 |
Detailed Energy Space Exploration | p. 255 |
Software Implementation | p. 256 |
Predicting Software Performance via Sampling | p. 258 |
Multicore Issues | p. 261 |
A Practical Methodology for Multi-processor ASIP Definition and Programming | p. 262 |
Developing Multicore System-Level Models | p. 265 |
Porting Methodology for New Video Codecs to the Multicore system | p. 265 |
Using the IDE for Multicore Simulation and Validation | p. 267 |
Debug | p. 268 |
Single-Core Debug in the IDE | p. 268 |
Multi-processor Debug in the IDE | p. 268 |
Conclusions | p. 272 |
References | p. 272 |
Codesign Experiences Based on a Virtual Platform | p. 273 |
Introduction | p. 273 |
Virtual Platforms | p. 274 |
Introduction | p. 274 |
Evolution of Platform Complexity | p. 274 |
Methodologies | p. 275 |
Commercial Technologies for Virtual Platform Development | p. 277 |
Models of Computation | p. 280 |
Platform and Application Description | p. 281 |
System Specification and Functional Verification | p. 282 |
Architectural Exploration | p. 284 |
Analysis | p. 292 |
Integration | p. 297 |
Experiments | p. 300 |
Pipelined vs. Non-pipelined Models | p. 300 |
Architectural Exploration of the JPEG Decoder | p. 302 |
Conclusion | p. 305 |
References | p. 307 |
Transaction-Level Platform Creation | p. 309 |
Introduction | p. 309 |
Transaction-Level Modeling Comes of Age | p. 311 |
Model Abstractions | p. 312 |
Terminology | p. 312 |
Model Taxonomy | p. 313 |
Roles of the TLM Platform | p. 315 |
Contextual Verification | p. 317 |
Creating Models | p. 319 |
Model Refinement | p. 320 |
Multi-abstraction | p. 323 |
Verification | p. 325 |
Timing | p. 333 |
Timing Policies | p. 335 |
Delay | p. 335 |
Split | p. 336 |
Sequential | p. 337 |
Pipelining | p. 338 |
Putting it all Together | p. 339 |
Timing Callbacks | p. 341 |
Power | p. 342 |
Creating a Model | p. 342 |
Using Model Builder | p. 342 |
Synchronization | p. 345 |
Integrating 3rd party Models | p. 346 |
Model Abstraction | p. 346 |
Building a System | p. 346 |
Navigating a System | p. 347 |
Example | p. 348 |
Building the System | p. 350 |
Running the Simulation | p. 351 |
Analyzing the System | p. 354 |
Inserting an ISS Model | p. 356 |
Conclusions | p. 358 |
References | p. 359 |
C/C++ Hardware Design for the Real World | p. 361 |
Introduction | p. 361 |
Chapter Overview | p. 362 |
Where Does it Fit in an ESL Flow | p. 363 |
Hardware Implementation Input | p. 365 |
High-Level Synthesis Output | p. 367 |
Verification Models | p. 368 |
Other Uses for the Input Model | p. 369 |
Why C/C++/SystemC | p. 369 |
Language Limitations for Synthesis | p. 372 |
High-Level Synthesis Fundamentals | p. 373 |
Schedule and Allocation Trade-offs | p. 373 |
Synthesis at the Interface | p. 375 |
Hierarchy | p. 375 |
Other Control | p. 376 |
Target Library | p. 378 |
Data-Type Libraries for Synthesis | p. 378 |
Synthesis Tools | p. 382 |
Synthesis Domains | p. 385 |
A Simple Example | p. 385 |
Embedded Architecture | p. 386 |
Tying It into a Verification Flow | p. 392 |
Verification with Simulation | p. 392 |
Verification with Equivalence Checking | p. 394 |
Verification Against Algorithmic Model | p. 394 |
Verifying Power | p. 396 |
A More Complex Example | p. 397 |
The Application | p. 398 |
The Flow | p. 399 |
Design | p. 400 |
Verification | p. 415 |
Synthesis | p. 417 |
Results | p. 423 |
Results Analysis | p. 425 |
Successful Adoption | p. 426 |
The Future | p. 428 |
Summary | p. 429 |
References | p. 430 |
Acronyms | p. 433 |
Index | p. 437 |
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