Fundamentals of Parallel Multicore Architecture

Perspectives on Multicore Architectures The Origin of the Multicore Architecture Perspectives on Parallel Computers Future Multicore Architectures Perspectives on Parallel Programming Limits on Parallel Program Performance Parallel Programming Models Shared Memory Parallel Programming Steps in Parallel Programming Dependence Analysis Identifying Parallel Tasks in Loop Structures Identifying Parallelism at Other Levels Identifying Parallelism through Algorithm Knowledge Determining the Scope of Variables Synchronization Assigning Tasks to Threads Mapping Threads to Processors A Brief Introduction to OpenMP Parallel Programming for Linked Data Structures Parallelization Challenges in LDS Approaches to Parallelization of LDS Parallelization Techniques for Linked Lists The Role of Transactional Memory Introduction to Memory Hierarchy Organization Motivation for Memory Hierarchy Basic Architectures of a Cache Cache Performance Prefetching Cache Design in Multicore Architecture Physical Cache Organization Logical Cache Organization Introduction to Shared Memory Multiprocessors The Cache Coherence Problem Memory Consistency Problem Synchronization Problem Cache Coherence Protocol Basic Issues Overview Cache Coherence in Bus-Based Multiprocessors Impact of Cache Design on Cache Coherence Performance Performance and Other Practical Issues Broadcast Protocol with Point-to-Point Interconnect Hardware Support for Synchronization Lock Implementations Barrier Implementations Transactional Memory Memory Consistency Models Programmers' Intuition Architecture Mechanisms for Ensuring Sequential Consistency Relaxed Consistency Models Synchronization in Different Memory Consistency Models Cache Coherence Protocol Advanced Issues Directory Coherence Protocols Overview of Directory Coherence Protocol Basic Directory Cache Coherence Protocol Implementation Correctness and Performance Contemporary Design Issues Interconnection Network Architecture Link, Channel, and Latency Network Topology Routing Policies and Algorithms Router Architecture Case Study: Alpha 21364 Network Architecture Multicore Design Issues SIMT Architecture SIMT Programming Model Mapping SIMT Workloads to SIMT Cores SIMT Core Architecture Ask the Experts Exercises appear at the end of each chapter.