Preface | p. xi |
Acronyms | p. xiii |
Sets, Relations, Logic Functions | p. 1 |
Sets | p. 1 |
Relations | p. 2 |
Functions | p. 4 |
Representations of Logic Functions | p. 9 |
SOP and POS expressions | p. 13 |
Positional Cube Notation | p. 16 |
Factored Expressions | p. 17 |
Exercises and Problems | p. 19 |
Algebraic Structures for Logic Design | p. 21 |
Algebraic Structure | p. 21 |
Finite Groups | p. 21 |
Finite Rings | p. 24 |
Finite Fields | p. 25 |
Homomorphisms | p. 27 |
Matrices | p. 30 |
Vector spaces | p. 33 |
Algebra | p. 37 |
Boolean Algebra | p. 38 |
Boolean expressions | p. 40 |
Graphs | p. 42 |
Exercises and Problems | p. 44 |
Functional Expressions for Switching Functions | p. 47 |
Shannon Expansion Rule | p. 50 |
Reed-Muller Expansion Rules | p. 51 |
Fast Algorithms for Calculation of RM-expressions | p. 56 |
Negative Davio Expression | p. 57 |
Fixed Polarity Reed-Muller Expressions | p. 59 |
Algebraic Structures for Reed-Muller Expressions | p. 62 |
Interpretation of Reed-Muller Expressions | p. 63 |
Kronecker Expressions | p. 64 |
Generalized bit-level expressions | p. 67 |
Word-Level Expressions | p. 68 |
Arithmetic expressions | p. 70 |
Calculation of Arithmetic Spectrum | p. 73 |
Applications of ARs | p. 74 |
Walsh Expressions | p. 77 |
Walsh Functions and Switching Variables | p. 80 |
Walsh Series | p. 80 |
Relationships Among Expressions | p. 82 |
Generalizations to Multiple-Valued Functions | p. 85 |
Exercises and Problems | p. 87 |
Decision Diagrams for Representation of Switching Functions | p. 89 |
Decision Diagrams | p. 89 |
Decision Diagrams over Groups | p. 97 |
Construction of Decision Diagrams | p. 99 |
Shared Decision Diagrams | p. 102 |
Multi-terminal binary decision diagrams | p. 103 |
Functional Decision Diagrams | p. 103 |
Kronecker decision diagrams | p. 108 |
Pseudo-Kronecker decision diagrams | p. 110 |
Spectral Interpretation of Decision Diagrams | p. 112 |
Spectral transform decision diagrams | p. 112 |
Arithmetic spectral transform decision diagrams | p. 114 |
Walsh decision diagrams | p. 115 |
Reduction of Decision Diagrams | p. 119 |
Exercises and Problems | p. 122 |
Classification of Switching Functions | p. 125 |
NPN-classification | p. 126 |
SD-Classification | p. 129 |
LP-classification | p. 133 |
Universal Logic Modules | p. 137 |
Exercises and Problems | p. 145 |
Synthesis with Multiplexers | p. 147 |
Synthesis with Multiplexers | p. 149 |
Optimization of Multiplexer Networks | p. 151 |
Networks with Different Assignments of Inputs | p. 153 |
Multiplexer Networks from BDD | p. 154 |
Applications of Multiplexers | p. 157 |
Demultiplexers | p. 162 |
Synthesis with Demultiplexers | p. 162 |
Applications of Demultiplexers | p. 166 |
Exercises and Problems | p. 168 |
Realizations with Rom | p. 171 |
Realizations with ROM | p. 171 |
Two-level Addressing in ROM Realizations | p. 176 |
Characteristics of Realizations with ROM | p. 180 |
Exercises and Problems | p. 181 |
Realizations with Programmable Logic Arrays | p. 183 |
Realizations with PLA | p. 184 |
The optimization of PLA | p. 186 |
Two-level Addressing of PLA | p. 189 |
Folding of PLA | p. 191 |
Minimization of PLA by Characteristic Functions | p. 194 |
Exercises and Problems | p. 196 |
Universal Cellular Arrays | p. 199 |
Features of Universal Cellular Arrays | p. 199 |
Realizations with Universal Cellular Arrays | p. 201 |
Synthesis with Macro Cells | p. 205 |
Exercises and Problems | p. 208 |
Field Programmable Logic Arrays | p. 211 |
Synthesis with FPGAs | p. 221 |
Synthesis with Antifuse-Based FPGAs | p. 222 |
Synthesis with LUT-FPGAs | p. 224 |
Design procedure | p. 225 |
Exercises and Problems | p. 233 |
Boolean Difference and Applications in Testing Logic Networks | p. 235 |
Boolean difference | p. 236 |
Properties of the Boolean Difference | p. 237 |
Calculation of the Boolean Difference | p. 238 |
Boolean Difference in Testing Logic Networks | p. 242 |
Errors in combinatorial logic networks | p. 242 |
Boolean difference in generation of test sequences | p. 246 |
Easily Testable Logic Networks | p. 250 |
Features of Easily Testable Networks | p. 251 |
Easily Testable Realizations from PPRM-expressions | p. 251 |
Easily Testable Realizations from GRM-expressions | p. 257 |
Related Work, Extensions, and Generalizations | p. 263 |
Exercises and Problems | p. 265 |
Sequential Networks | p. 269 |
Basic Sequential Machines | p. 271 |
State Tables | p. 274 |
Conversion of Sequential Machines | p. 277 |
Minimization of States | p. 278 |
Incompletely Specified Machines | p. 281 |
State Assignment | p. 283 |
Decomposition of Sequential Machines | p. 287 |
Serial Decomposition of Sequential Machines | p. 287 |
Parallel Decomposition of Sequential Machines | p. 290 |
Exercises and Problems | p. 294 |
Realization of Sequential Networks | p. 297 |
Memory Elements | p. 298 |
Synthesis of Sequential Networks | p. 302 |
Realization of Binary Sequential Machines | p. 304 |
Realization of Synchronous Sequential Machines | p. 306 |
Pulse Mode Sequential Networks | p. 309 |
Asynchronous Sequential Networks | p. 313 |
Races and Hazards | p. 318 |
Race | p. 319 |
Hazards | p. 320 |
Exercises and Problems | p. 322 |
References | p. 325 |
Index | p. 339 |
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