Hardware Design and Simulation in VAL/VHDL

I A Tutorial Introduction to VAL.- 1 Introduction.- 1.1 Comparative Simulation With VAL.- 1.2 Why Extend VHDL?.- 1.3 Future Directions.- 1.4 Notation and Conventions.- 2 An Overview of VAL.- 2.1 Entity Annotations.- 2.1.1 Entity State Model.- 2.1.2 Assumptions.- 2.1.3 Statements and Processes.- 2.1.4 Timing Behavior.- 2.2 Architecture Annotations.- 2.3 Configuration Annotations.- 3 Timing Models.- 3.1 The VHDL Timing Model.- 3.1.1 Unit Delay.- 3.1.2 Transport Delay.- 3.1.3 Inertial Delay.- 3.1.4 Justification.- 3.2 The VAL Timing Model.- 3.2.1 Anticipatory Semantics.- 3.2.2 Assertions.- 4 Designing With Annotations.- 4.1 Introduction.- 4.2 Traffic Light Controller.- 4.2.1 Specification.- 4.2.2 Implementation.- 4.3 Stack.- 4.3.1 Specification.- 4.3.2 Implementation.- 4.4 Summary.- II Examples.- 5 Crazy AND Gate.- 5.1 Requirements.- 5.2 Entity Declaration.- 5.3 Commentary.- 5.3.1 Altering the Specification.- 5.3.2 Altering the Implementation.- 6 D-Type Flip-flop.- 6.1 Requirements.- 6.2 Entity Declaration.- 6.3 Commentary.- 7 Traffic Light Controller.- 7.1 Requirements.- 7.2 Entity Declaration.- 7.3 Architecture.- 7.4 Simulation Results.- 8 Stack.- 8.1 Requirements.- 8.2 Entity Declaration.- 8.3 Entity Architecture.- 8.4 Commentary.- 9 Water Heater Controller.- 9.1 Requirements.- 9.2 Entity Declaration.- 9.3 Implementation.- 9.4 Simulation Results.- 10 CPU Example.- 10.1 Requirements.- 10.1.1 Instruction level specification.- 10.1.2 Register transfer level specifications.- 10.1.3 Gate level specifications.- 10.1.4 Hierarchy of components.- 10.2 CPU Annotation methodology.- 10.2.1 Entity annotation.- 10.2.2 Mapping.- 10.3 VHDL description.- III The VAL Language Reference Manual.- 11 Lexical Elements.- 11.1 Character Set.- 11.2 Lexical Elements, Separators, and Delimiters.- 11.3 Identifiers.- 11.4 Literals.- 11.5 Comments.- 11.6 Annotations.- 11.7 Reserved Words.- 11.8 Allowable Replacements of Characters.- 11.9 BNF Notation.- 12 Design Units.- 12.1 Entity Annotations.- 12.2 Architecture Annotations.- 12.3 Configuration Annotations.- 13 State Model.- 13.1 State Model Declaration.- 13.2 State Model Type.- 14 Declarations.- 14.1 Types, Subtypes, Constants, Aliases and Use Clauses.- 14.2 Assumptions.- 14.3 Objects.- 14.4 Macros.- 15 Names and Expressions.- 15.1 Timed Expressions.- 15.2 Intervals.- 15.3 Function Call.- 16 Statements.- 16.1 Assertions.- 16.2 Drive Statement.- 16.3 Guards.- 16.4 Select.- 16.5 Generate.- 16.6 Macro Call.- 16.7 Null.- 17 Mapping Annotations.- 18 Configuration Annotations.- 19 Miscellaneous.- 19.1 Package.- 19.2 Scope and Visibility.- 19.2.1 Declarative Region and Scope of Declarations.- 19.2.2 Visibility.- 19.2.3 Use Clause.- 19.2.4 The Context of Overload Resolution.- 19.3 Attributes.- IV Transformer Implementation Guide.- 20 The VAL Transformer.- 20.1 Transformation Principles.- 20.2 Translation Methodology.- 20.3 Transformation Algorithm.- 20.3.1 Generation of Translation Skeleton.- 20.3.2 Transformation to Core VAL.- 20.3.3 Code Generation.- 20.3.4 Architecture Annotations.- 20.3.5 Configuration Annotations.- 20.4 Summary.- V Appendix.- A Syntax Summary.- A.1 Lexical Elements.- A.2 Syntax.- B CPU : VHDL description.- B.1 One bit alu.- B.2 16 bit alu.- B.3 One bit buffer.- B.4 12 bit buffer.- B.5 16 bit buffer.- B.6 CPU.- B.7 CPU configuration.- B.8 CPU support package.- B.9 CPU test bench.- B.10 Or arrays.- B.11 PLA.- B.12 One bit one output register.- B.13 16 bit one output register.- B.14 One bit two output register.- B.15 16 bit two output register.