High Level Synthesis of ASICs under Timing and Synchronization Constraints

By: David C. Ku, Giovanni DeMicheli

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Hardcover | 31 May 1992

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Hardcover
312 Pages

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24.77 x 16.51 x 2.54

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Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers.
High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book.
Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

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You Can Find This Book In

Non-Fiction Computing & I.T.Graphical & Digital Media Applications Computer-Aided Design CAD Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Energy Technology & Engineering Electrical Engineering

Introduction	p. 1
Overview of High-level Synthesis	p. 2
Motivation and Issues in High-level Synthesis	p. 3
Research Objectives	p. 6
Summary of Related Work	p. 13
Assumptions and Limitations	p. 16
Outline of the Book	p. 16
System Overview	p. 19
Modeling Hardware Behavior	p. 19
Overview of the Synthesis Flow	p. 42
Behavioral Transformations	p. 47
Behavioral Intermediate Form	p. 48
User-driven Behavioral Transformations	p. 49
Automatic Behavioral Transformations	p. 51
Summary of Behavioral Transformations	p. 60
Sequencing Graph and Resource Model	p. 61
Basic Definitions	p. 62
Timing Constraints	p. 69
Hardware Resources	p. 75
Summary of Sequencing Graph Model	p. 80
Design Space Exploration	p. 83
Design Space Formulation	p. 85
Concurrency Factor	p. 93
Design Space Exploration Strategy	p. 102
Summary of Design Space Exploration	p. 110
Relative Scheduling	p. 113
Introduction to Scheduling	p. 117
Relative Scheduling Formulation	p. 118
Algorithms for Relative Scheduling	p. 141
Analysis of Algorithms	p. 156
Summary of Relative Scheduling	p. 161
Resource Conflict Resolution	p. 163
Conflict Resolution Formulation	p. 164
Constraint Topology	p. 166
Algorithms for Conflict Resolution	p. 174
Summary of Conflict Resolution	p. 181
Relative Control Generation	p. 183
Adaptive Control Approach	p. 187
Relative Control Approach	p. 204
Summary of Control Generation	p. 212
Relative Control Optimization	p. 213
Control Optimization Criterion	p. 214
Redundancy in Synchronization	p. 217
Control Optimization Approach	p. 223
Analysis of Control Resynchronization	p. 234
Summary of Control Resynchronization	p. 235
System Implementation	p. 237
Overview of Hercules	p. 239
Overview of Hebe	p. 243
Summary of System Implementation	p. 252
Experimental Results	p. 253
Design Experiences	p. 254
Synthesis of Benchmark Examples	p. 270
Summary of Experimental Results	p. 273
Conclusions and Future Work	p. 275
Future Work	p. 277
References	p. 281
Index	p. 291
Table of Contents provided by Blackwell. All Rights Reserved.

High Level Synthesis of ASICs under Timing and Synchronization Constraints

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Hardcover

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