| Keynote Speech | |
| Connecting E-Dreams to Deep-Submicron Realities | p. 1 |
| Invited Talks | |
| Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization | p. 2 |
| Low-Voltage Embedded RAMs - Current Status and Future Trends | p. 3 |
| Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing | p. 16 |
| Embedded Tutorials | |
| Leakage in CMOS Circuits - An Introduction | p. 17 |
| The Certainty of Uncertainty: Randomness in Nanometer Design | p. 36 |
| Buses and Communication | |
| Crosstalk Cancellation for Realistic PCB Buses | p. 48 |
| A Low-Power Encoding Scheme for GigaByte Video Interfaces | p. 58 |
| Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures | p. 69 |
| Perfect 3-Limited-Weight Code for Low Power I/O | p. 79 |
| A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses | p. 90 |
| Circuits and Devices (I) | |
| Performance Metric Based Optimization Protocol | p. 100 |
| Temperature Dependence in Low Power CMOS UDSM Process | p. 110 |
| Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques | p. 119 |
| High Yield Standard Cell Libraries: Optimization and Modeling | p. 129 |
| A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits | p. 138 |
| Low Power (I) | |
| Sleepy Stack Reduction of Leakage Power | p. 148 |
| A Cycle-Accurate Energy Estimator for CMOS Digital Circuits | p. 159 |
| Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures | |
| Reducing Cross-Talk Induced Power Consumption and Delay | p. 179 |
| Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell | p. 189 |
| Leakage Power Analysis and Comparison of Deep Submicron Logic Gates | p. 198 |
| Architectures | |
| Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS | p. 208 |
| Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications | p. 218 |
| Register Isolation for Synthesizable Register Files | p. 228 |
| Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures | p. 238 |
| Design of High-Speed Low-Power Parallel-Prefix VLSI Adders | p. 248 |
| Asynchronous Circuits | |
| GALSification of IEEE 802.11a Baseband Processor | p. 258 |
| TAST Profiler and Low Energy Asynchronous Design Methodology | p. 268 |
| Low Latency Synchronization Through Speculation | p. 278 |
| Minimizing the Power Consumption of an Asynchronous Multiplier | p. 289 |
| A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling | p. 301 |
| System Design | |
| L0 Cluster Synthesis and Operation Shuffling | p. 311 |
| On Combined DVS and Processor Evaluation | p. 322 |
| A Multi-level Validation Methodology for Wireless Network Applications | p. 332 |
| SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level | p. 342 |
| Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards | p. 352 |
| Towards a Software Power Cost Analysis Framework Using Colored Petri Net | p. 362 |
| Circuits and Devices (II) | |
| A 260ps Quasi-static ALU in 90nm CMOS | p. 372 |
| Embedded EEPROM Speed Optimization Using System Power Supply Resources | p. 381 |
| Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption | p. 392 |
| A Predictive Synchronizer for Periodic Clock Domains | p. 402 |
| Power Supply Net for Adiabatic Circuits | p. 413 |
| Interconnect and Physical Design | |
| A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI | p. 423 |
| Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery | p. 433 |
| An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design | p. 442 |
| Wirelength Reduction Using 3-D Physical Design | p. 453 |
| On Skin Effect in On-Chip Interconnects | p. 463 |
| Security and Safety | |
| A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits | p. 471 |
| A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors | p. 481 |
| A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design | p. 491 |
| The Impact of Low-Power Techniques on the Design of PortableSafety-Critical Systems | p. 501 |
| Low Power (II) | |
| Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems | p. 510 |
| PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures | p. 521 |
| Power Consumption of Performance-Scaled SIMD Processors | p. 532 |
| Low Effort, High Accuracy Network-on-Chip Power Macro Modeling | p. 541 |
| Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling | p. 553 |
| Low-Power Processing (Poster) | |
| Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers | p. 564 |
| Power Aware Dividers in FPGA | p. 574 |
| A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses | p. 585 |
| The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms | p. 593 |
| Low Power Co-design Tool and Power Optimization of Schedules and Memory System | p. 603 |
| Hardware Building Blocks of a Mixed Granularity ReconfigurableSystem-on-Chip Platform | p. 613 |
| Enhancing GALS Processor Performance Using Data Classification Based on Data Latency | p. 623 |
| Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors | p. 633 |
| Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems | p. 643 |
| Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path | p. 652 |
| Power Estimation for Ripple-Carry Adders with Correlated Input Data | p. 662 |
| LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS | p. 675 |
| Digital Design (Poster) | |
| Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits | p. 685 |
| A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic | p. 691 |
| Pipelines in Dynamic Dual-Rail Circuits | p. 701 |
| Optimum Buffer Size for Dynamic Voltage Processors | p. 711 |
| Design Optimization with Automated Cell Generation | p. 722 |
| A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool | p. 732 |
| A Novel Constant-Time Fault-Secure Binary Counter | p. 742 |
| Buffer Sizing for Crosstalk Induced Delay Uncertainty | p. 750 |
| Optimal Logarithmic Representation in Terms of SNR Behavior | p. 760 |
| A New Logic Transformation Method for Both Low Power and High Testability | p. 770 |
| Energy-Efficient Hardware Architecture for Variable N-point 1D DCT | p. 780 |
| Modeling and Simulation (Poster) | |
| Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits | p. 789 |
| A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment | p. 799 |
| Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis | p. 809 |
| On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects | p. 819 |
| Signal Sampling Based Transition Modeling for Digital Gates Characterization | p. 829 |
| Physical Extension of the Logical Effort Model | p. 838 |
| An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies | p. 849 |
| Moment-Based Estimation of Switching Activity for Correlated Distributions | p. 859 |
| Table-Based Total Power Consumption Estimation of Memory Arrays for Architects | p. 869 |
| A Physically Oriented Model to Quantify the Noise-on-Delay Effect | p. 879 |
| Noise Margin in Low Power SRAM Cells | p. 889 |
| Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic | p. 899 |
| Author Index | p. 907 |
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