| Keynote Speech | |
| Architectural Challenges for the Next Decade Integrated Platforms | p. 1 |
| Gate-Level Modeling and Design | |
| Analysis of High-Speed Logic Families | p. 2 |
| Low-Voltage, Double-Edge-Triggered Flip Flop | p. 11 |
| A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems | p. 21 |
| State Encoding for Low-Power FSMs in FPGA | p. 31 |
| Low Level Modeling and Characterization | |
| Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies | p. 41 |
| A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates | p. 51 |
| CMOS Gate Sizing under Delay Constraint | p. 60 |
| Process Characterization for Low VTH and Low Power Design | p. 70 |
| Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results | p. 80 |
| Interconnect Modeling and Optimization | |
| Effects of Temperature in Deep-Submicron Global Interconnect Optimization | p. 90 |
| Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits | p. 101 |
| Estimation of Crosstalk Noise for On-Chip Buses | p. 111 |
| A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization | p. 121 |
| Interconnect Driven Low Power High-Level Synthesis | p. 131 |
| Asynchronous Techniques | |
| Bridging Clock Domains by Synchronizing the Mice in the Mousetrap | p. 141 |
| Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization | p. 151 |
| New GALS Technique for Datapath Architectures | p. 161 |
| Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders | p. 171 |
| Statistic Implementation of QDI Asynchronous Primitives | p. 181 |
| Keynote Speech | |
| The Emergency of Design for Energy Efficiency: An EDA Perspective | p. 192 |
| Industrial Session | |
| The Most Complete Mixed-Signal Simulation Solution with ADVance MS | p. 193 |
| Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips | p. 194 |
| Power Management in Synopsys Galaxy Design Platform | p. 195 |
| Open Multimedia Platform for Next-Generation Mobile Devices | p. 196 |
| RTL Power Modeling and Memory Optimisation | |
| Statistical Power Estimation of Behavioral Descriptions | p. 197 |
| A Statistic Power Model for Non-synthetic RTL Operators | p. 208 |
| Energy Efficient Register Renaming | p. 219 |
| Stand-by Power Reduction for Storage Circuits | p. 229 |
| A Unified Framework for Power-Aware Design of Embedded Systems | p. 239 |
| High-Level Modeling | |
| A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems | p. 249 |
| High Level Area and Current Estimation | p. 259 |
| Switching Activity Estimation in Non-linear Architectures | p. 269 |
| Instruction Level Energy Modeling for Pipelined Processors | p. 279 |
| Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level | p. 289 |
| Power Efficient Technologies and Designs | |
| An Adiabatic Charge Pump Based Charge Recycling Design Style | p. 299 |
| Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing | p. 309 |
| Low Power Response Time Accelerator with Full Resolution for LCD Panel | p. 319 |
| Memory Compaction and Power Optimization for Wavelet-Based Coders | p. 328 |
| Design Space Exploration and Trade-Offs in Analog Amplifier Design | p. 338 |
| Keynote Speech | |
| Power and Timing Driven Physical Design Automation | p. 348 |
| Communication Modeling and Design | |
| Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks | p. 358 |
| Remote Power Control of Wireless Network Interfaces | p. 369 |
| Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders | p. 379 |
| A Fully Digital Numerical-Controlled-Oscillator | p. 389 |
| Low Power Issues in Processors and Multimedia | |
| Energy Optimization of High-Performance Circuits | p. 399 |
| Instruction Buffering Exploration for Low Energy Embedded Processors | p. 409 |
| Power-Aware Branch Predictor Update for High-Performance Processors | p. 420 |
| Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms | p. 430 |
| High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder | p. 440 |
| Poster Session 1 | |
| Metric Definition for Circuit Speed Optimization | p. 451 |
| Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies | p. 461 |
| An Asynchronous Viterbi Decoder for Low-Power Applications | p. 471 |
| Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits | p. 481 |
| A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application | p. 491 |
| Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits | p. 501 |
| Poster Session 2 | |
| A Pratical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages | p. 511 |
| Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus | p. 520 |
| Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction | p. 530 |
| A Bottom-Up Approach to On-Chip Signal Integrity | p. 540 |
| Advanced Cell Modeling Techniques Based on Polynomial Expressions | p. 550 |
| RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches | p. 559 |
| Poster Session 3 | |
| Data Dependences Critical Path Evaluation at C/C++ System Level Description | p. 569 |
| A Hardware/Sofware Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements | p. 580 |
| Consideration of Control System and Memory Contributions in Pratical Resource-Constrained Scheduling for Low Power | p. 590 |
| Low Power Cache with Successive Tag Comparison Algorithm | p. 599 |
| FPGA Architecture Design and Toolset for Logic Implementation | p. 607 |
| Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis | p. 617 |
| Author Index | p. 629 |
| Table of Contents provided by Publisher. All Rights Reserved. |
