Introduction to Advanced System-on-Chip Test Design and Optimization

By: Erik Larsson

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Hardcover | 7 November 2005

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SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.

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Preface	p. xiii
Acknowledgements	p. xvii
Testing concepts
Introduction	p. 1
Design Flow	p. 5
Introduction	p. 5
High-level design	p. 6
Core-Based Design	p. 7
Network-on-Chip	p. 9
Platform-Based Design	p. 9
Clocking	p. 10
System Timing	p. 11
Clock Distribution	p. 11
Multiple Clock Domains	p. 12
Phase Locked Loop (PLL)	p. 12
Globally-Asynchronous Locally-Synchronous	p. 13
Optimization	p. 14
Optimization Techniques	p. 16
Backtracking and Branch-and-bound	p. 16
Integer Linear Programming	p. 17
Local Search	p. 17
Simulated Annealing	p. 18
Genetic Algorithms	p. 18
Tabu Search	p. 19
Design for Test	p. 21
Introduction	p. 21
Fault models	p. 21
Stuck-at Fault Model	p. 22
Bridging Fault Model	p. 22
Stuck-Open Fault Model	p. 23
Delay Fault Model	p. 23
Test Generation for Combinational Circuits	p. 24
Path Sensitization	p. 25
Boolean Difference	p. 25
D-algorithm	p. 26
PODEM (Path-Oriented Decision-Making)	p. 27
FAN (Fanout-Oriented Test Generation)	p. 28
Subscripted D-Algorithm	p. 28
CONcurrent Test Generation	p. 28
Fault Simulation	p. 28
Optimization	p. 28
Delay Fault Detection	p. 30
Testing Sequential Circuits	p. 30
Design-for-Test Methods	p. 31
Test Point Insertion	p. 32
The Scan Technique	p. 32
Scan Testing for Delay Faults	p. 36
Test Pattern Generation for BIST	p. 39
Exhaustive Pattern Generation	p. 40
Pseudo-Random Pattern Generation	p. 40
Pseudo-random-based test generation	p. 40
Deterministic Testing	p. 41
Test Response Analysis for BIST	p. 41
Circular-BIST	p. 43
BIST-Architectures	p. 43
BILBO (Built-In Logic Block Observer)	p. 43
STUMPS Architecture	p. 44
LOCST (LSSD On-Chip Self-Test)	p. 44
Memory Testing	p. 45
Algorithmic Test Sequence (ATS)	p. 48
Marching Pattern Sequences (MARCH)	p. 48
Checkboard Test	p. 49
Memory BIST	p. 49
Memory Diagnosis and Repair	p. 50
Mixed-Signal Testing	p. 51
Boundary Scan	p. 53
Introduction	p. 53
The Boundary-Scan Standards (IEEE 1149.1)	p. 53
Registers	p. 56
TAP Controller	p. 57
Instructions	p. 57
Example	p. 57
Boundary-Scan Languages	p. 58
Cost of Boundary Scan	p. 58
Analog Test Bus (IEEE 1149.4)	p. 61
Analog Test Access Port (ATAP)	p. 63
Test Bus Interface Circuit (TBIC)	p. 63
Analog Boundary Module (ABM)	p. 63
Instructions	p. 63
Chaining Example	p. 63
SOC Design for Testability
System Modeling	p. 67
Introduction	p. 67
Core modeling	p. 68
Test Resource modeling	p. 71
Core Wrapper	p. 72
Test Access Mechanism	p. 74
Test Conflicts	p. 77
Introduction	p. 77
Limitations at the Tester	p. 78
Bandwidth Limitations	p. 79
Tester Memory Limitations	p. 79
Test Channel Clocking	p. 80
Test Conflicts	p. 81
General Test Conflicts	p. 81
Multiple Test Set	p. 82
Multiple Sets of Test Sets	p. 82
Interconnection Testing - Cross-Core Testing	p. 84
Hierarchy - Cores Embedded in Cores	p. 85
Discussion	p. 86
Test Power Dissipation	p. 89
Introduction	p. 89
Power consumption	p. 90
System-level Power modeling	p. 91
Hot-spot modeling with Power Grids	p. 93
Core-level Power modeling	p. 95
Discussion	p. 98
Test Access Mechanism	p. 99
Introduction	p. 99
System-on-Chip Test Data Transportation	p. 100
The TestShell and P1500 Approach	p. 100
Reconfigurable Core Wrappers	p. 106
Test Access Mechanism Design	p. 107
Multiplexing Architecture	p. 108
Distribution Architecture	p. 109
Daisychain Architecture	p. 110
Test Bus Architecture	p. 111
TestRail Architecture	p. 111
Flexible-Width Architecture	p. 112
Core Transparancy	p. 112
Test TIME Analysis	p. 113
Test Scheduling	p. 115
Introduction	p. 115
scheduling of Tests with fixed test time under test conflicts	p. 119
Preemptive test scheduling	p. 128
scheduling of tests with non-fixed (variable) testing times	p. 128
Idle Types	p. 128
Imbalanced TAM Test Completion Times	p. 129
Module Assigned to TAM of Non Pareto Optimal Width	p. 130
Imbalanced Scan Chains in Module	p. 131
Other Types of Idle Bits	p. 131
SOC Test Scheduling with Fixed-Width TAM	p. 132
SOC Test Scheduling with Flexible-Width TAM	p. 134
Test Power	p. 137
Multiple Test Sets	p. 138
Other Test Scheduling Techniques	p. 138
Problem: Control lines and Layout	p. 138
Problem: Power Modeling	p. 138
Problem: Fixed Test Resources	p. 139
Problem: Multiple Clock Domains	p. 140
Problem: Delay Fault Testing	p. 140
Defect-Oriented Scheduling	p. 140
Optimal Test time?	p. 143
Soft Cores - No Fixed Scan-Chains	p. 146
Hard Cores - Fixed Number of Scan-chains	p. 150
Integrated Test Scheduling and TAM Design	p. 151
Test Time and Test Power Consumption	p. 152
Bandwidth Assignment	p. 152
Test Scheduling	p. 153
TAM Planning	p. 154
TAM Optimization	p. 156
Integrating Core Selection in the Test Design Flow	p. 157
Further Studies	p. 160
Combined Test Time and TAM Design Minimization	p. 160
Core Selection in the Test Design Flow	p. 160
Defect-Oriented Test Scheduling	p. 160
SOC Test Applications
A Reconfigurable Power-Conscious Core Wrapper and Its Application to System-on-Chip Test Scheduling	p. 163
Introduction	p. 163
Background and Related Work	p. 165
A Reconfigurable Power-Conscious Core Wrapper	p. 167
Optimal Test Scheduling	p. 170
Optimal Scheduling of Core Tests	p. 171
Transformations for Optimal TAM Utilization	p. 173
Cross-Core Test Scheduling	p. 175
Optimal Power-Constrained Scheduling	p. 177
Minimization of TAM Wiring	p. 179
Experimental Results	p. 180
Conclusions	p. 182
An Integrated Framework for the Design and Optimization of Soc Test Solutions	p. 187
Introduction	p. 187
Related Work	p. 188
System modeling	p. 192
The SOC Test Issues	p. 194
Test Scheduling	p. 194
Power Consumption	p. 195
Test Source Limitations	p. 197
Test Set Selection	p. 197
Test Access Mechanism	p. 198
Test Floor-planning	p. 200
The Heuristic Algorithm	p. 201
Simulated Annealing	p. 205
The Simulated Annealing Algorithm	p. 205
Initial Solution and Parameter Selection	p. 206
Neighbouring Solution in Test Scheduling	p. 206
Neighbouring Solution in Scheduling and TAM Design	p. 206
Cost function	p. 207
Experimental Results	p. 208
Benchmarks	p. 208
Test Scheduling	p. 208
Test Resource Placement	p. 209
Test Access Mechanism Design	p. 209
Test Scheduling and TAM Design	p. 211
Conclusions	p. 214
Efficient Test Solutions for Core-Based Designs	p. 215
Introduction	p. 215
Introduction	p. 215
Background and Related Work	p. 217
Test Problems	p. 221
Test Time	p. 221
Test Power Consumption	p. 226
Test Power Consumption at Test Parallelization	p. 229
Test Resource Limitations	p. 230
Test Conflicts	p. 231
Test Access Mechanism Design	p. 232
System Modeling	p. 233
Our Approach	p. 237
Bandwidth Assignment	p. 238
Test Scheduling	p. 239
TAM Planning	p. 240
An Example	p. 242
TAM Optimization	p. 244
Complexity	p. 246
Experimental Results	p. 246
Test Scheduling	p. 246
Integrated Test Scheduling and TAM Design	p. 247
Test Scheduling, Test Parallelization and TAM Design	p. 249
Conclusions	p. 250
Core Selection in the Soc Test Design-Flow	p. 253
Introduction	p. 253
Background	p. 254
Related Work	p. 257
Problem Formulation	p. 260
Problem Complexity	p. 263
Test Problems and Their Modeling	p. 263
Test Time	p. 263
Test Power Consumption	p. 264
Test Conflicts	p. 267
Test Design Algorithm	p. 268
Resource Utilization	p. 271
Example	p. 271
Experimental Results	p. 273
Conclusions	p. 275
Defect-Aware Test Scheduling	p. 277
Introduction	p. 277
Related Work	p. 278
Sequential Test Scheduling	p. 279
Concurrent Test Scheduling	p. 280
Test Sets with Fixed Test Times	p. 281
Test Sets with Flexible Test Times	p. 282
Test Scheduling Algorithms	p. 283
Experimental Results	p. 286
Conclusions	p. 286
An Integrated Technique for Test Vector Selection and Test Scheduling Under Ate Memory Depth Constraint	p. 291
Introduction	p. 291
Related Work	p. 293
Problem Formulation	p. 295
Test Quality Metric	p. 296
Test Scheduling and Test Vector Selection	p. 299
Illustrative Example	p. 301
Optimal Solution For Single TAM	p. 305
Experimental Results	p. 305
Conclusions	p. 307
Benchmarks	p. 321
Introduction	p. 321
Format of the inputfile	p. 321
Design Kime	p. 324
Design Muresan 10	p. 326
Design Muresan 20	p. 327
ASIC Z	p. 329
Extended ASIC Z	p. 331
System L	p. 333
Ericsson design	p. 335
System S	p. 349
References	p. 353
Index	p. 383
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Introduction to Advanced System-on-Chip Test Design and Optimization

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Hardcover

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