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Loop Tiling for Parallelism

By: Jingling Xue

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Hardcover | 31 August 2000

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Hardcover
280 Pages

Dimensions(cm)
23.39 x 15.6 x 1.75

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Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines.
Features and key topics:

Detailed review of the mathematical foundations, including convex polyhedra and cones;
Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;
Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;
A complete suite of techniques for generating SPMD code for a tiled loop nest;
Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;
End-of-chapter references for further reading.

Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.

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You Can Find This Book In

Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Parallel Processing Computer Programming & Software Development Compilers & Interpreters Databases Data Capture & Analysis Medicine Medicine in General Business Applications

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Paperback

Published: 12th October 2012

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List of Figures	p. ix
List of Tables	p. xiii
Preface	p. xv
Acknowledgments	p. xix
Mathematic Background and Loop Transformation
Mathematical Background	p. 3
Logic	p. 3
Sets	p. 4
Arithmetic	p. 4
Vectors and Matrices	p. 4
Roots of Cubic and Quartic Equations	p. 6
Integer Matrices	p. 11
Convex Analysis	p. 17
Convex Polyhedra	p. 19
Convex Cones	p. 20
Fourier-Motzkin Elimination	p. 28
Further Reading	p. 32
Nonsingular Transformations and Permutability	p. 35
Perfectly Nested Loops	p. 36
Dependence Vectors and Their Polyhedra	p. 38
Iteration-Reordering Transformations	p. 43
Fully Permutable Loop Nests	p. 59
Further Reading	p. 67
Tiling as a Loop Transformation
Rectangular Tiling	p. 73
Modeling Rectangular Tiling	p. 74
Legality Test	p. 78
Tile Dependences and Title Space Graph	p. 85
Tiled Code	p. 85
Tiling-Related Transformations	p. 87
Yet Another Tiling Model	p. 94
Further Reading	p. 96
Parallelepiped Tiling	p. 101
Why Parallelepiped Tiling?	p. 102
Legality Test	p. 107
Tile Dependences and Tile Space Graph	p. 113
Tiled Code	p. 113
Decomposition of Parallelepiped Tiling	p. 113
Yet Another Tiling Model	p. 116
Loop Partitioning v.s. Loop Tiling	p. 118
Further Reading	p. 120
Tiling for Distributed-Memory Machines
Spmd Code Generation	p. 123
Background	p. 124
Machine Model	p. 130
Computation Distribution	p. 131
Data Distribution	p. 133
I/O Code Generation	p. 134
Message-Passing Code Generation	p. 137
Memory Management	p. 146
SPMD Code in Local Address Space	p. 156
SPMD Code for Parallelepiped Tiling	p. 158
Experiments	p. 160
Further Reading	p. 168
Communication-Minimal Tiling	p. 169
Computation and Communication Volumes	p. 172
Problem Formulation	p. 176
Closed-Form Optimal Tilings	p. 179
All Extremal-Ray Optimal Tilings	p. 187
Making H[superscript -1] Integral	p. 196
Further Reading	p. 196
Time-Minimal Tiling	p. 199
Parallelogram Tiling	p. 199
Executing Tiles in the SPMD Paradigm	p. 201
Computation and Communication Models	p. 202
Rise	p. 204
Optimal Tile Size	p. 204
Experiments	p. 233
Further Reading	p. 245
Bibliography	p. 247
Index	p. 255
Table of Contents provided by Syndetics. All Rights Reserved.

Loop Tiling for Parallelism

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Hardcover

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