Author Bios | p. xiii |
FPGA Overview: Architecture and CAD | p. 1 |
Introduction | p. 2 |
FPGA Logic Resources Architecture | p. 5 |
Altera Stratix IV Logic Resources | p. 6 |
Xilinx Virtex-5 Logic Resources | p. 7 |
Actel ProASIC3/IGLOO Logic Resources | p. 8 |
Actel Axcelerator Logic Resources | p. 9 |
FPGA Routing Resources Architecture | p. 10 |
CAD for FPGAs | p. 12 |
Logic Synthesis | p. 12 |
Packing | p. 13 |
Placement | p. 14 |
Timing Analysis | p. 16 |
Routing | p. 16 |
Versatile Place and Route (VPR) CAD Tool | p. 17 |
VPR Architectural Assumptions | p. 17 |
Basic Logic Packing Algorithm: VPack | p. 22 |
Timing-Driven Logic Block Packing: T-VPack | p. 24 |
Placement: VPR | p. 26 |
Routing: VPR | p. 28 |
Power Dissipation in Modern FPGAs | p. 31 |
CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits | p. 32 |
Dynamic Power in FPGAs | p. 35 |
Leakage Power in FPGAs | p. 35 |
CMOS Device Leakage Mechanisms | p. 35 |
Current Situation of Leakage Power in Nanometer FPGAs | p. 38 |
Power Estimation in FPGAs | p. 41 |
Introduction | p. 42 |
Power Estimation in VLSI: An Overview | p. 44 |
Simulation-Based Power Estimation Techniques | p. 44 |
Probabilistic-Based Power Estimation Techniques | p. 47 |
Commercial FPGA Power Estimation Techniques | p. 50 |
Spreadsheet Power Estimation Tools | p. 50 |
CAD Power Estimation Tools | p. 51 |
A Survey of FPGA Power Estimation Techniques | p. 53 |
Linear Regression-Based Power Modeling | p. 54 |
Probabilistic FPGA Power Models | p. 56 |
Look-up Table-Based FPGA Power Models | p. 56 |
A Complete Analytical FPGA Power Model under Spatial Correlation | p. 58 |
Spatial Correlation and Signal Probability Calculations | p. 58 |
Exploration Phase: Locating Spatial Correlation | p. 60 |
Signal Probabilities Calculation Algorithm under Spatial Correlation | p. 61 |
Power Calculations Due to Glitches | p. 65 |
Signal Probabilities and Power Dissipation | p. 66 |
Results and Discussion | p. 71 |
Dynamic Power Reduction Techniques in FPGAs | p. 85 |
Multiple Supply Voltages | p. 86 |
Predefined Dual-VDD Dual-Vth FPGAs | p. 87 |
Programmable Dual-VDD | p. 92 |
Other Dual-VDD FPGA Techniques | p. 97 |
Reducing Glitches in FPGAs. | p. 99 |
Glitch Power Reduction Using Delay Insertion | p. 99 |
Multiphase Flip-Flop Insertion for Glitch Power Reduction in FPGAs | p. 105 |
Negative Edge Flip-Flop Insertion for Glitch Power Reduction in FPGAs | p. 115 |
Behavioral Synthesis with Flip-Flop Insertion for Glitch Power Reduction in FPGAs | p. 117 |
CAD Techniques for Reducing Dynamic Power in FPGAs | p. 122 |
Power Reduction Techniques during Technology Mapping | p. 122 |
Power Reduction Techniques during Clustering | p. 132 |
Power Reduction Techniques during Placement and Routing | p. 134 |
Leakage Power Reduction in FPGAs Using MTCMOS Techniques | p. 139 |
Introduction | p. 140 |
MTCMOS FPGA Architecture | p. 143 |
Sleep Transistor Design and Discharge Current Processing | p. 148 |
Sleep Transistor Sizing | p. 148 |
Mutually Exclusive Discharge Current Processing | p. 151 |
Logic-Based Discharge Current Processing | p. 153 |
Topological Sorting and Discharge Current Addition | p. 154 |
Activity Profile Generation | p. 158 |
Connection-Based Activity Profile Generation Algorithm (CAP) | p. 160 |
LAP Generation | p. 166 |
Activity Packing Algorithms | p. 174 |
AT-VPack | p. 175 |
Force-Based Activity T-VPack (FAT-VPack) | p. 177 |
Timing-Driven MTCMOS (T-MTCMOS) AT-VPack | p. 178 |
Power Estimation | p. 180 |
Results and Discussion | p. 181 |
Experimental Setup | p. 182 |
Algorithm Comparison | p. 183 |
Impact of Activity Packing on Performance | p. 186 |
Leakage Savings Breakdown | p. 189 |
Impact of Utilization and ON Time on Leakage Savings | p. 191 |
Impact of the Sleep Region Size | p. 193 |
Scalability of the Proposed Algorithms with Technology Scaling | p. 194 |
Leakage Power Reduction in FPGAs Through Input Pin Reordering | p. 195 |
Leakage Power and Input State Dependency in FPGAs | p. 197 |
Subthreshold Leakage Current | p. 197 |
Gate Leakage | p. 200 |
Low-Leakage States in Pass-Transistor Multiplexers | p. 201 |
Leakage Power in Inverters/Buffers | p. 203 |
Proposed Input Pin Reordering Algorithm | p. 204 |
LPR Algorithm | p. 205 |
Routing Switch Pin Reordering (RPR) Algorithm | p. 210 |
Experimental Results | p. 212 |
Pin Reordering and Performance | p. 215 |
Pin Reordering and Technology Scaling | p. 218 |
Conclusion | p. 219 |
References | p. 221 |
Index | p. 237 |
Table of Contents provided by Ingram. All Rights Reserved. |