Multi-voltage CMOS Circuit Design

List of Figures.

Preface.

1 Introduction.

1.1 Evolution of Integrated Circuits.

1.2 Outline of the Book.

2 Sources of Power Consumption in CMOS Integrated Circuits.

2.1 Dynamic Switching Power.

2.2 Leakage Power.

2.3 Short-Circuit Power.

2.4 Static DC Power.

3 Supply and Threshold Voltage Scaling Techniques.

3.1 Dynamic Supply Voltage Scaling.

3.2 Multiple Supply Voltage CMOS.

3.3 Threshold Voltage Scaling.

3.4 Multiple Supply and Threshold Voltage CMOS.

3.5 Dynamic Supply and Threshold Voltage Scaling.

3.6 Circuits with Multiple Voltage and Clock Domains.

3.7 Chapter Summary.

4 Low Voltage Power Supplies.

4.1 Linear DC-DC Converters.

4.2 Switched-Capacitor DC-DC Converters.

4.3 Switching DC-DC Converters.

4.4 Chapter Summary.

5 Analysis of Buck Converters for On-Chip Integration with a Dual Supply Voltage Microprocessor.

5.1 Circuit Model of a Buck Converter.

5.2 Efficiency Analysis of a Buck Converter.

5.3 Simulation Results.

5.4 Chapter Summary.

6 Low Voltage Swing Monolithic DC-DC Conversion.

6.1 Circuit Model of a Low Voltage Swing Buck Converter.

6.2 Low Voltage Swing Buck Converter Analysis.

6.3 Chapter Summary.

7 High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.

7.1 Cascode Bridge Circuits.

7.2 High Input Voltage Monolithic Switching DC-DC Converters.

7.3 Chapter Summary.

8 Signal Transfer in Integrated Circuits with Multiple Supply Voltages.

8.1 A High Speed and Low Power Voltage Interface Circuit.

8.2 Voltage Interface Circuit Simulation Results.

8.3 Experimental Results.

8.4 Chapter Summary.

9 Domino Logic with Variable Threshold Voltage Keeper.

9.1 Standard Domino Logic Circuits.

9.2 Domino Logic with Variable Threshold Voltage Keeper.

9.3 Simulation Results.

9.4 Domino Logic with Forward and Reverse Body Biased Keeper.

9.5 Chapter Summary.

10 Subthreshold Leakage Current Characteristics of Dynamic Circuits.

10.1 State Dependent Subthreshold Leakage Current Characteristics.

10.2 Noise Immunity.

10.3 Power and Delay Characteristics in the Active Mode.

10.4 Dual Threshold Voltage CMOS Technology.

10.5 Chapter Summary.

11Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Standby Leakage Current.

11.1 Previously Published Sleep Mode Circuit Techniques.

11.2 Dual Threshold Voltage Domino Logic Employing Sleep Switches.

11.3 Simulation Results.

11.4 Noise Immunity Compensation.

11.5 Chapter Summary.

12 Conclusions.

Bibliography.

Index.

About the Authors.