Practical Computing on the Cell Broadband Engine

Cover -- Contents -- Part I: Introducing the Cell Broadband Engine -- 1 Introduction -- 1.1 About this book -- 1.2 Background of the CBE Architecture and Processor -- 1.3 Design of the Cell Architecture -- 1.4 The Cell as a supercomputer -- 1.5 Major Components of the Cell Broadband Engine -- 1.6 Flex I/O, DDR/XDR, Interrupt Controller -- 1.7 Conclusions -- 2 The Power Processing Element (PPE) -- 2.1 PPE: the Control Plane of the CBEA -- 2.2 PPE Problem State Registers -- 2.3 Memory arrays in the CBEA -- 2.4 Viewing the PPE as a dual-core processor: EMT specifics -- 2.5 PowerPC Instruction Set -- 2.6 SPE Memory Management and EA Aliasing -- 2.7 Power Processor Element (PPE) Cache Utilization -- 2.8 Understanding the PPE Pipeline -- 2.9 Measuring and Profiling Application Performance -- 2.10 Conclusion -- 3 The Synergistic Processing Element -- 3.1 Introduction to Cell SPE -- 3.2 SPE Local Store -- 3.3 SPU LS Priority -- 3.4 GPRs in the SPE -- 3.5 SPE Intrinsics and Instruction -- 3.6 SPU Instruction Set: Pipelines, Execution Units and Latency -- 3.7 Load/Store Optimization on SPU -- 3.8 Branch Optimization on SPU -- 3.9 Instruction Scheduling -- 3.10 Memory flow -- 3.11 Mailbox Facility -- 3.12 Use SPU Intrinsics with Mailboxes -- 3.13 Synergistic Processor Unit Channels and Memory Flow Controller -- 3.14 SPU Timer and Events -- 3.15 SPE Context on the PPE -- 3.16 Conclusion -- 3.17 What we have not discussed -- 4 Element Interconnect Bus -- 4.1 Introduction to the Element Interconnect Bus -- 4.2 Important things to remember about the EIB -- 4.3 Conclusions -- 5 Direct Memory Access (DMA) -- 5.1 Introduction to DMA in the Cell Broadband Engine -- 5.2 Conclusions -- Part II: Programming the Cell Broadband Engine -- 6 Foundations for Program Development on CBE -- 6.1 Theory of Parallel Programming -- 6.2 The Class NC of complexity analysis -- 6.3 Parallel programming concepts -- 6.4 Introduction to pthreads -- 6.5 Multi-faceted parallelism in the CBE Architecture -- 6.6 Alignment using compiler attributes -- 6.7 OpenMP -- 6.8 Double buffering example -- 6.9 Software Managed Cache -- 6.10 Physical Organization -- 6.11 Things to watch out for -- 6.12 Strategies and Paradigms for Identifying Parallelism -- 6.13 Conclusion -- 7 The development environment -- 7.1 How to setup an PS3 for Cell development -- 7.2 Alternatives to installing GNU/Linux on the PS3 -- 7.3 The CESOF Format -- 7.4 Basic development environment -- 7.5 Debugging code on the SPU -- 7.6 Conclusions -- 8 Hello World -- 8.1 Writing simple programs on the Cell Broadband Engine -- 8.2 SPE Program Development -- 8.3 Using pthread with SPU tasks -- 8.4 Developing applications using libspe2 -- 8.5 Measuring Performance using High Resolution Timers -- 8.6 Synchronization -- 8.7 Conclusions -- 9 An Overview of the SDK -- 9.1 Major components of the Cell Broadband Engine SDK 3.0 -- 9.2 Application programming libraries in the SDK -- 9.3 SPE Runtime Library -- 9.4 SPU Timer Library -- 9.5 Monte-Carlo Library -- 9.6 BLAS Library -- 9.7 LAPACK Library -- 9.8 SIMD Math API and Library -- 9.9 SPU Software Managed Cache -- 9.10 FFT Library -- 9.11 Game Math Library -- 9.12 Image Library -- 9.13 Large Matrix Library -- 9.14 Matrix Library -- 9.15.