Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms

Cover -- Copyright -- Dedication -- Contents -- Foreword -- Preface -- 1. Introduction -- 1.1 Challenge: From Board to SoC -- 1.2 Degrees of SoC Customization -- 1.2.1 Computation -- 1.2.2 Communication -- 1.3 Organization of this Book -- 2. SoC Design Methodologies -- 2.1 Traditional HW/SW Co-Design -- 2.1.1 HW/SW Co-Simulation -- 2.1.2 Automatic Synthesis -- 2.2 System Level Design -- 2.2.1 Motivation -- 2.2.2 Standardization -- 2.2.3 Design Flows -- 2.3 Current Research on SoC Design Methodologies -- 2.3.1 Bottom-Up SoC Design -- 2.3.2 Top-Down SoC Design -- 2.4 Contribution of this Work -- 3. Communication Modeling -- 3.1 Transaction Level Modeling -- 3.1.1 Use Cases -- 3.1.2 Abstraction Levels -- 3.2 Generic Communication Modeling -- 3.2.1 Architects View Framework (AVF) -- 3.2.2 Generic TLM Simulation Modules -- 3.3 Communication Customization -- 3.3.1 Communication IP Providers -- 3.3.2 Protocol Specific TLM Interfaces -- 3.4 The BusCompiler Tool -- 3.4.1 Cycle Accurate Communication Modeling -- 3.4.2 BusCompiler Input Specification -- 4. Processor Modeling -- 4.1 Generic Processor Modeling -- 4.1.1 Native Execution on the Simulation Host -- 4.1.2 Generic Assembly Level -- 4.2 Processor Customization Techniques -- 4.2.1 Selectable Processor Core IP -- 4.2.2 (Re- )Configurable Processor Architectures -- 4.2.3 ADLs -- 4.3 LISA -- 4.3.1 LISA Processor Design Platform -- 4.3.2 Abstraction Levels -- 4.3.3 LISA 2.0 Input Specification -- 5. Processor System Integration -- 5.1 Simulator Structure -- 5.1.1 Standalone Processor Simulator -- 5.1.2 The LISA Bus Interface -- 5.1.3 SystemC Wrapper -- 5.2 Adaptors: Bridging Abstraction Gaps -- 5.2.1 LISA Bus/Memory API -- 5.2.2 TLM Communication Module API -- 5.2.3 API Mapping -- 5.2.4 Bus Interface State Machine -- 5.3 Commercial SoC Simulation Environments -- 5.3.1 CoWare PlatformArchitect System Simulator -- 5.3.2 Synopsys SystemStudio SoC Simulator -- 6. Sucessive Top-Down Refinement Flow -- 6.1 Phase 1: Standalone -- 6.1.1 SoC Communication -- 6.1.2 LISA Standalone -- 6.2 Phase 2: IA ASIPAVF Communication Models -- 6.3 Phase 3: IA ASIPCA TLM Bus -- 6.4 Phase 4: CA ASIPCA TLM Bus -- 6.5 Phase 5: BCA ASIPCA TLM Bus -- 6.6 Phase 6: RTL ASIPCA TLM Bus 78 -- 6.7 Phase 7: RTL ASIPRTL Bus -- 7. Automatic Retargetability -- 7.1 MP-SoC Simulator Generation Chain -- 7.2 Structure of the Generated Simulator -- 7.2.1 Creating the Communication Infrastructure -- 7.2.2 Generating SystemC Processor Models -- 7.2.3 Generating Adaptors -- 7.3 Bus Interface Specification -- 7.3.1 Overview -- 7.3.2 Feeding Data into the State Machine -- 7.3.3 Characterizing the State Machine -- 7.3.4 Getting Data Out of the State Machine -- 7.3.5 Advantages -- 8. Debugging and Profiling -- 8.1 Multi-Processor Debugger -- 8.1.1 Retargetable Standalone Simulation -- 8.1.2 Multi-Processor Synchronization -- 8.1.3 Dynamic Connect -- 8.1.4 Source Code Level Debugging with GNU gdb -- 8.2 TLM Bus Traffic Visualization -- 8.2.1 Message Sequence Charts (MSC) -- 8.2.2 Word Level Data Display -- 8.3 Bus Interface Analysis -- 8.3.1 CoWare PlatformArchitect Analysis -- 8.