Robust Sigma Delta Converters

List of abbreviations. Terminology. List of symbols. Nomenclature. 1 Introduction. 1.1 Advanced, multi-standard cellular and connectivity terminals for the mass market. 1.2 Book aims. 1.3 Book scope. 1.4 Original contributions. 1.5 Outline. 2 System quality indicators. 2.1 The system function and its in- and outputs. 2.2 System quality. 2.3 The digital revolution. 2.4 Conclusions. 3 Integrated receiver architectures for cellular and connectivity. 3.1 Wireless receiver architectures for digital Communications. 3.2 Receiver architecture and the quality indicators. 3.3 Conclusions. 4 Specifications for A/D converters in cellular and connectivity receivers. 4.1 IF choice. 4.2 Top-end of the ADC DR. 4.3 Receiver gain. 4.4 Bottom-end of the ADC DR. 4.5 DR of the ADC. 4.6 RF front-end and ADC linearity requirements. 4.7 Example receiver partitioning: receiver for a GSM mobile phone. 4.8 ADC requirements, the system quality indicators and SD modulators as the ADC architecture. 4.9 Conclusions. 5 SD modulator algorithmic accuracy. 5.1 SD modulators with 1-bit quantizer and 1-bit DAC. 5.2 SD modulators with b-bit quantizer and b-bit DAC. 5.3 SD modulators with 1.5-bit quantizer and DAC. 5.4 SD modulators with multiple quantizers and 1-bit DAC. 5.5 SD modulators with additive error-feedback loops. 5.6 Cascaded SD modulators. 5.7 Conclusions. 6 SD modulator robustness. 6.1 Portable, technology robust analog IP and time-to-market. 6.2 Continuous time vs. discrete time loop filter. 6.3 Feed-forward vs. feedback loop filter. 6.4 Gain accuracy. 6.5 Circuit noise of the modulator's input stage and DAC. 6.6 Non-linearity. 6.7 Aliasing in SD modulators. 6.8 Excess loop delay. 6.9 Clock jitter in CT SD modulators. 6.10 Conclusions. 7 SD modulator flexibility. 7.1 Receiver dictated flexibility requirements. 7.2 SD modulator clock flexibility. 7.3 Input stage and DAC flexibility. 7.4 Loop-filter flexibility. 7.5 Quantizer flexibility. 7.6 Conclusions. 8 SD modulator efficiency. 8.1 Power efficiency FOM: FOMDR. 8.2 Power efficiency FOM: FOMeq,th. 8.3 Distortion FOM: FOMHD3D. 8.4 Area FOM: FOMarea. 8.5 Conclusions. 9 SD modulator implementations and the quality indicators. 9.1 Digitization at system/application level: SD modulators for highly digitized receivers. 9.2 Digitization at analog IP architecture level: a hybrid, inverter based SD modulator. 9.3 Digitization at circuit and layout level: technology portable SD Modulators. 9.4 Implementations judged on the FOMs and quality indicators. 9.5 Conclusions. 10 Conclusions. A Harmonic and intermodulation distortion in an I&Q system. A.1 Double sided spectrum of second and third order distortion of a complex signal. A.2 Double sided spectrum of second and third order distortion in a complex system. B Distortion of a differential input transistor pair biased in weak inversion. C Fourier series expansion and return-to-zero. D Clock jitter in an I&Q system according to the TPJE clock jitter model. References. Index.