Results for author 'Rolf Drechsler'

Evolutionary Algorithms for VLSI CAD

Advanced Formal Verification

Falk Symposium Ser.

Evolutionary Algorithms for VLSI CAD

Advanced Formal Verification

Towards a Design Flow for Reversible Logic

Test Pattern Generation using Boolean Proof Engines

Formal System Verification

State-of the-Art and Future Trends

Advanced Logic Synthesis

Reversible and Quantum Circuits

Optimization and Complexity Analysis

Information Storage

A Multidisciplinary Perspective

In-Memory Computing

Synthesis and Optimization

Recent Findings in Boolean Techniques

Selected Papers from the 14th International Workshop on Boolean Problems

Design for Testability, Debug and Reliability

Next Generation Measures Using Formal Techniques

Information Storage

A Multidisciplinary Perspective

Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes

Better Early than Never

Formal System Verification

State-of the-Art and Future Trends

Languages, Design Methods, and Tools for Electronic System Design

Selected Contributions from FDL 2015

Reversible and Quantum Circuits

Optimization and Complexity Analysis

Automated Analysis of Virtual Prototypes at the Electronic System Level

Design Understanding and Applications

Design Automation Techniques for Approximation Circuits

Verification, Synthesis and Test

Enhanced Virtual Prototyping

Featuring RISC-V Case Studies

Advanced Boolean Techniques

Selected Papers from the 13th International Workshop on Boolean Problems

Advanced Boolean Techniques

Selected Papers from the 15th International Workshop on Boolean Problems

Formal Verification of Structurally Complex Multipliers

Design for Testability, Debug and Reliability

Next Generation Measures Using Formal Techniques