| Preface | p. xi |
| Review of Combinational Logic | p. 1 |
| Number Systems | p. 2 |
| Binary Number System | p. 3 |
| Octal Number System | p. 4 |
| Decimal Number System | p. 4 |
| Hexadecimal Number System | p. 5 |
| Number Representations | p. 8 |
| Sign Magnitude | p. 8 |
| Diminished-Radix Complement | p. 9 |
| Radix Complement | p. 10 |
| Boolean Algebra | p. 12 |
| Minimization Techniques | p. 18 |
| Algebraic Minimization | p. 19 |
| Karnaugh Maps | p. 20 |
| Quine-McCluskey Algorithm | p. 28 |
| Logic Symbols | p. 35 |
| Analysis of Combinational Logic | p. 37 |
| Synthesis of Combinational Logic | p. 42 |
| Multiplexers | p. 45 |
| Decoders | p. 47 |
| Encoders | p. 53 |
| Comparators | p. 54 |
| Storage Elements | p. 56 |
| SR Latch | p. 57 |
| D Flip-Flop | p. 57 |
| JK Flip-Flop | p. 59 |
| T Flip-Flop | p. 60 |
| Programmable Logic Devices | p. 61 |
| Programmable Read-Only Memories | p. 61 |
| Programmable Array Logic | p. 64 |
| Programmable Logic Array | p. 67 |
| Problems | p. 69 |
| Analysis of Synchronous Sequential Machines | p. 77 |
| Sequential Circuits | p. 78 |
| Machine Alphabets | p. 79 |
| Formal Definition of a Synchronous Sequential Machine | p. 82 |
| Classes of Sequential Machines | p. 89 |
| Combinational Logic | p. 89 |
| Registers | p. 93 |
| Counters | p. 98 |
| Moore Machines | p. 105 |
| Mealy Machines | p. 110 |
| Asynchronous Sequential Machines | p. 121 |
| Additional Definitions for Synchronous Sequential Machines | p. 123 |
| Methods of Analysis | p. 136 |
| Next-State Table | p. 136 |
| Present-State Map | p. 137 |
| Next-State Map | p. 137 |
| Input Map | p. 138 |
| Output Map | p. 140 |
| Timing Diagram | p. 141 |
| State Diagram | p. 143 |
| Analysis Examples | p. 146 |
| Complete and Incomplete Synchronous Sequential Machines | p. 161 |
| Complete Synchronous Sequential Machines | p. 161 |
| Incomplete Synchronous Sequential Machines | p. 162 |
| Problems | p. 166 |
| Synthesis of Synchronous Sequential Machines 1 | p. 181 |
| Synthesis Procedure | p. 182 |
| Equivalent States | p. 183 |
| Synchronous Registers | p. 197 |
| Parallel-In, Parallel-Out Registers | p. 197 |
| Parallel-In, Serial-Out Registers | p. 201 |
| Serial-In, Parallel-Out Registers | p. 205 |
| Serial-In, Serial-Out Registers | p. 208 |
| Linear Feedback Shift Registers | p. 212 |
| Combinational Shifter | p. 218 |
| Synchronous Counters | p. 223 |
| Modulo-8 Counter | p. 223 |
| Modulo-10 Counter | p. 234 |
| Johnson Counter | p. 245 |
| Binary-to-Gray Code Converter | p. 248 |
| Moore Machines | p. 254 |
| Mealy Machines | p. 277 |
| Moore-Mealy Equivalence | p. 298 |
| Mealy-to-Moore Transformation | p. 298 |
| Moore-to-Mealy Transformation | p. 307 |
| Output Glitches | p. 307 |
| Glitch Elimination Using State Code Assignment | p. 312 |
| Glitch Elimination Using Storage Elements | p. 319 |
| Glitch Elimination Using Complemented Clock | p. 323 |
| Glitch Elimination Using Delayed Clock | p. 326 |
| Glitches and Output Maps | p. 333 |
| Compendium of Output Glitches | p. 339 |
| Problems | p. 344 |
| Synthesis of Synchronous Sequential Machines 2 | p. 361 |
| Multiplexers for [delta] Next-State Logic | p. 361 |
| Linear-Select Multiplexers | p. 363 |
| Nonlinear-Select Multiplexers | p. 377 |
| Decoders for [lambda] Output Logic | p. 400 |
| Programmable Logic Devices | p. 412 |
| Programmable Read-Only Memory | p. 413 |
| Programmable Array Logic | p. 421 |
| Programmable Logic Array | p. 432 |
| Field-Programmable Gate Array | p. 437 |
| Microprocessor-Controlled Sequential Machines | p. 448 |
| General Considerations | p. 449 |
| Mealy Machine Synthesis | p. 453 |
| Machine State Augmentation | p. 461 |
| Moore and Mealy Outputs | p. 466 |
| System Architecture | p. 467 |
| Multiple Machines | p. 477 |
| Sequential Iterative Machines | p. 481 |
| Error Detection in Synchronous Sequential Machines | p. 489 |
| Problems | p. 500 |
| Analysis of Asynchronous Sequential Machines | p. 519 |
| Introduction | p. 520 |
| Fundamental-Mode Model | p. 522 |
| Methods of Analysis | p. 526 |
| Hazards | p. 553 |
| Static Hazards | p. 553 |
| Dynamic Hazards | p. 568 |
| Essential Hazards | p. 572 |
| Multiple-Order Hazards | p. 577 |
| Oscillations | p. 578 |
| Races | p. 582 |
| Noncritical Races | p. 583 |
| Cycles | p. 586 |
| Critical Races | p. 586 |
| Problems | p. 590 |
| Synthesis of Asynchronous Sequential Machines | p. 607 |
| Introduction | p. 608 |
| Synthesis Procedure | p. 610 |
| State Diagram | p. 612 |
| Primitive Flow Table | p. 616 |
| Equivalent States | p. 632 |
| Merger Diagram | p. 645 |
| Merged Flow Table | p. 656 |
| Excitation Maps and Equations | p. 661 |
| Output Maps and Equations | p. 691 |
| Logic Diagram | p. 710 |
| Synthesis Examples | p. 716 |
| Mealy Machine with Two Inputs and One Output | p. 716 |
| Mealy Machine with Two Inputs and One Output Using a Programmable Logic Array (PLA) | p. 727 |
| Moore Machine with One Input and One Output | p. 735 |
| Mealy Machine with Two Inputs and Two Outputs | p. 741 |
| Mealy Machine with Three Inputs and One Output | p. 755 |
| Mealy Machine with Two Inputs and Two Outputs | p. 765 |
| Problems | p. 777 |
| Pulse-Mode Asynchronous Sequential Machines | p. 807 |
| Analysis Procedure | p. 809 |
| SR Latches as Storage Elements | p. 810 |
| SR Latches with D Flip-Flops as Storage Elements | p. 817 |
| Synthesis Procedure | p. 823 |
| SR Latches as Storage Elements | p. 823 |
| T Flip-Flops as Storage Elements | p. 830 |
| SR-T Flip-Flops as Storage Elements | p. 836 |
| SR Latches with D Flip-Flops as Storage Elements | p. 844 |
| Problems | p. 850 |
| Answers to Selected Problems | p. 861 |
| Index | p. 889 |
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