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Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

By: Ruijing Shen, Sheldon X.-D. Tan, Hao Yu

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Hardcover | 19 March 2012

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Hardcover
336 Pages

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23.39 x 15.6 x 1.91

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Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have become imperative for the successful design of VLSI chips.

This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.

Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits;
Helps chip designers understand the potential and limitations of their design tools, improving their design productivity;
Presents analysis of each algorithm with practical applications in the context of real circuit design;
Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.

Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits;
Helps chip designers understand the potential and limitations of their design tools, improving their design productivity;
Presents analysis of each algorithm with practical applications in the context of real circuit design;
Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Mathematics Algebra Technology in General Nanotechnology Industrial Chemistry & Manufacturing Technologies Other Manufacturing Technologies Precision Instruments Manufacture

Computing & I.T.Graphical & Digital Media Applications Computer-Aided Design CAD

Fundamentals
Introduction	p. 3
Nanometer Chip Design in Uncertain World	p. 3
Causes of Variations	p. 4
Process Variation Classification and Modeling	p. 6
Process Variation Impacts	p. 8
Book Outline	p. 8
Statistical Full-Chip Power Analysis	p. 9
Variational On-Chip Power Delivery Network Analysis	p. 10
Statistical Interconnect Modeling and Extraction	p. 11
Statistical Analog and Yield Analysis and Optimization	p. 12
Summary	p. 13
Fundamentals of Statistical Analysis	p. 15
Basic Concepts in Probability Theory	p. 15
Experiment, Sample Space, and Event	p. 15
Random Variable and Expectation	p. 16
Variance and Moments of Random Variable	p. 17
Distribution Functions	p. 18
Gaussian and Log-Normal Distributions	p. 19
Basic Concepts for Multiple Random Variables	p. 20
Multiple Random Variables and Variable Reduction	p. 23
Components of Covariance in Process Variation	p. 23
Random Variable Decoupling and Reduction	p. 25
Principle Factor Analysis Technique	p. 26
Weighted PFA Technique	p. 26
Principal Component Analysis Technique	p. 27
Statistical Analysis Approaches	p. 28
Monte Carlo Method	p. 28
Spectral Stochastic Method Using Stochastic Orthogonal Polynomial Chaos	p. 29
Collocation-Based Spectral Stochastic Method	p. 31
Galerkin-Based Spectral Stochastic Method	p. 33
Sum of Log-Normal Random Variables	p. 33
Hermite PC Representation of Log-Normal Variables	p. 34
Hermite PC Representation with One Gaussian Variable	p. 35
Hermite PC Representation of Two and More Gaussian Variables	p. 35
Summary	p. 36
Statistical Full-Chip Power Analysis
Traditional Statistical Leakage Power Analysis Methods	p. 39
Introduction	p. 39
Static Leakage Modeling	p. 40
Gate-Based Static Leakage Model	p. 41
MOSFET-Based Static Leakage Model	p. 44
Process Variational Models for Leakage Analysis	p. 45
Full-Chip Leakage Modeling and Analysis Methods	p. 49
Monte Carlo Method	p. 49
Traditional Grid-Based Methods	p. 49
Projection-Based Statistical Analysis Methods	p. 53
Summary	p. 53
Statistical Leakage Power Analysis by Spectral Stochastic Method	p. 55
Introduction	p. 55
Flow of Gate-Based Method	p. 56
Random Variables Transformation and Reduction	p. 57
Computation of Full-Chip Leakage Currents	p. 58
Time Complexity Analysis	p. 60
Numerical Examples	p. 60
Summary	p. 63
Linear Statistical Leakage Analysis by Virtual Grid-Based Modeling	p. 65
Introduction	p. 65
Virtual Grid-Based Spatial Correlation Model	p. 67
Linear Chip-Level Leakage Power Analysis Method	p. 69
Computing Gate Leakage by the Spectral Stochastic Method	p. 70
Computation of Full-Chip Leakage Currents	p. 71
Time Complexity Analysis	p. 71
New Statistical Leakage Characterization in SCL	p. 72
Acceleration by Look-Up Table Approach	p. 72
Enhanced Algorithm	p. 73
Computation of Full-Chip Leakage Currents	p. 75
Incremental Leakage Analysis	p. 76
Time Complexity Analysis	p. 77
Discussion of Extension to Statistical Runtime Leakage Estimation	p. 77
Discussion about Runtime Leakage Reduction Technique	p. 79
Numerical Examples	p. 79
Accuracy and CPU Time	p. 80
Incremental Analysis	p. 82
Summary	p. 82
Statistical Dynamic Power Estimation Techniques	p. 83
Introduction	p. 83
Prior Works	p. 85
Existing Relevant Works	p. 85
Segment-Based Power Estimation Method	p. 86
The Presented New Statistical Dynamic Power Estimation Method	p. 87
Flow of the Presented Analysis Method	p. 87
Acceleration by Building the Look-Up Table	p. 88
Statistical Gate Power with Glitch Width Variation	p. 89
Computation of Full-Chip Dynamic Power	p. 89
Numerical Examples	p. 90
Summary	p. 92
Statistical Total Power Estimation Techniques	p. 93
Introduction	p. 93
Review of the Monte Carlo-Based Power Estimation Method	p. 95
The Statistical Total Power Estimation Method	p. 96
Flow of the Presented Analysis Method Under Fixed Input Vector	p. 97
Computing Total Power by Orthogonal Polynomials	p. 97
Flow of the Presented Analysis Method Under Random Input Vectors	p. 98
Numerical Examples	p. 99
Summary	p. 103
Variational On-Chip Power Delivery Network Analysis
Statistical Power Grid Analysis Considering Log-Normal Leakage Current Variations	p. 107
Introduction	p. 107
Previous Works	p. 108
Nominal Power Grid Network Model	p. 109
Problem Formulation	p. 111
Statistical Power Grid Analysis Based on Hermite PC	p. 112
Galerkin-Based Spectral Stochastic Method	p. 112
Spatial Correlation in Statistical Power Grid Analysis	p. 114
Variations in Wires and Leakage Currents	p. 115
Numerical Examples	p. 117
Comparison with Taylor Expansion Method	p. 118
Examples Without Spatial Correlation	p. 119
Examples with Spatial Correlation	p. 122
Consideration of Variations in Both Wire and Currents	p. 123
Summary	p. 126
Statistical Power Grid Analysis by Stochastic Extended Krylov Subspace Method	p. 127
Introduction	p. 127
Problem Formulation	p. 128
Review of Extended Krylov Subspace Method	p. 128
The Stochastic Extended Krylov Subspace MethodùStoEKS	p. 130
StoEKS Algorithm Flowchart	p. 130
Generation of the Augmented Circuit Matrices	p. 130
Computation of Hermite PCs of Current Moments with Log-Normal Distribution	p. 133
The StoEKS Algorithm	p. 135
A Walk-Through Example	p. 136
Computational Complexity Analysis	p. 137
Numerical Examples	p. 138
Summary	p. 143
Statistical Power Grid Analysis by Variational Subspace Method	p. 145
Introduction	p. 145
Review of Fast Truncated Balanced Realization Methods	p. 146
Standard Truncated Balanced Realization Methods	p. 146
Fast and Approximate TBR Methods	p. 147
Statistical Reduction by Variational TBR	p. 148
The Presented Variational Analysis Method: varETBR	p. 148
Extended Truncated Balanced Realization Scheme	p. 148
The Presented Variational ETBR Method	p. 150
Numerical Examples	p. 152
Summary	p. 158
Statistical Interconnect Modeling and Extractions
Statistical Capacitance Modeling and Extraction	p. 163
Introduction	p. 163
Problem Formulation	p. 165
Presented Orthogonal PC-Based Extraction Method: StatCap	p. 166
Capacitance Extraction Using Galerkin-Based Method	p. 166
Expansion of Potential Coefficient Matrix	p. 167
Formulation of the Augmented System	p. 170
Second-Order StatCap	p. 171
Derivation of Analytic Second-Order Potential Coefficient Matrix	p. 172
Formulation of the Augmented System	p. 173
Numerical Examples	p. 174
Additional Notes	p. 177
Summary	p. 182
Incremental Extraction of Variational Capacitance	p. 183
Introduction	p. 183
Review of GRMES and FMM Algorithms	p. 184
The GMRES Method	p. 184
The Fast Multipole Method	p. 184
Stochastic Geometrical Moment	p. 185
Geometrical Moment	p. 186
Orthogonal PC Expansion	p. 188
Parallel Fast Multipole Method with SGM	p. 189
Upward Pass	p. 190
Downward Pass	p. 191
Data Sharing and Communication	p. 191
Incremental GMRES	p. 193
Deflated Power Iteration	p. 194
Incremental Precondition	p. 194
piCAP Algorithm	p. 196
Extraction Flow	p. 196
Implementation Optimization	p. 198
Numerical Examples	p. 199
Accuracy Validation	p. 199
Speed Validation	p. 202
Eigenvalue Analysis	p. 205
Summary	p. 207
Statistical Inductance Modeling and Extraction	p. 209
Introduction	p. 209
Problem Formulation	p. 210
The Presented Statistical Inductance Extraction MethodùstatHenry	p. 212
Variable Decoupling and Reduction	p. 212
Variable Reduction by Weighted PEA	p. 213
Flow of statHenry Technique	p. 214
Numerical Examples	p. 214
Summary	p. 218
Statistical Analog and Yield Analysis and Optimization Techniques
Performance Bound Analysis of Variational Linearized Analog Circuits	p. 221
Introduction	p. 221
Review of Interval Arithmetic and Affine Arithmetic	p. 222
The Performance Bound Analysis Method Based on Graph-based Symbolic Analysis	p. 223
Variational Transfer Function Computation	p. 223
Performance Bound by Kharitonov's Functions	p. 228
Numerical Examples	p. 230
Summary	p. 233
Stochastic Analog Mismatch Analysis	p. 235
Introduction	p. 235
Preliminary	p. 237
Review of Mismatch Model	p. 237
Nonlinear Model Order Reduction	p. 237
Stochastic Transient Mismatch Analysis	p. 239
Stochastic Mismatch Current Model	p. 239
Perturbation Analysis	p. 240
Non-Monte Carlo Analysis by Spectral Stochastic Method	p. 240
A CMOS Transistor Example	p. 242
Macromodeling for Mismatch Analysis	p. 242
Incremental Trajectory-Piecewise-Linear Modeling	p. 243
Stochastic Extension for Mismatch Analysis	p. 246
Numerical Examples	p. 247
Comparison of Mismatch Waveform-Error and Runtime	p. 248
Comparison of TPWL Macromodel	p. 251
Summary	p. 252
Statistical Yield Analysis and Optimization	p. 253
Introduction	p. 253
Problem Formulations	p. 254
Stochastic Variation Analysis for Yield Analysis	p. 256
Algorithm Overview	p. 258
Stochastic Yield Estimation and Optimization	p. 259
Fast Yield Calculation	p. 259
Stochastic Sensitivity Analysis	p. 260
Multiobjective Optimization	p. 262
Numerical Examples	p. 265
NMC Mismatch for Yield Analysis	p. 266
Stochastic Yield Estimation	p. 266
Stochastic Sensitivity Analysis	p. 268
Stochastic Yield Optimization	p. 270
Summary	p. 272
Voltage Binning Technique for Yield Optimization	p. 273
Introduction	p. 273
Problem Formulation	p. 274
Yield Estimation	p. 274
Voltage Binning Problem	p. 275
The Presented Voltage Binning Method	p. 276
Voltage Binning Considering Valid Segment	p. 277
Bin Number Prediction Under Given Yield Requirement	p. 278
Yield Analysis and Optimization	p. 280
Numerical Examples	p. 281
Setting of Process Variation	p. 282
Prediction of Bin Numbers Under Yield Requirement	p. 282
Comparison Between Uniform and Optimal Voltage Binning Schemes	p. 283
Sensitivity to Frequency and Power Constraints	p. 284
CPU Times	p. 284
Summary	p. 285
References	p. 287
Index	p. 299
Table of Contents provided by Ingram. All Rights Reserved.

Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

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Hardcover

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