VLSI Design

Name: VLSI Design
Brand: Taylor & Francis Inc
Price: 224.5 AUD
Availability: BackOrder

By: M. Michael Vai

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Hardcover | 19 September 2000 | Edition Number 1

At a Glance

Hardcover
424 Pages

Dimensions(cm)
23.5 x 16.51 x 3.18

Hardcover

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Very Large Scale Integration (VLSI) has become a necessity rather than a specialization for electrical and computer engineers. This unique text provides Engineering and Computer Science students with a comprehensive study of the subject, covering VLSI from basic design techniques to working principles of physical design automation tools to leading edge application-specific array processors.

Beginning with CMOS design, the author describes VLSI design from the viewpoint of a digital circuit engineer. He develops physical pictures for CMOS circuits and demonstrates the top-down design methodology using two design projects - a microprocessor and a field programmable gate array. The author then discusses VLSI testing and dedicates an entire chapter to the working principles, strengths, and weaknesses of ubiquitous physical design tools. Finally, he unveils the frontiers of VLSI. He emphasizes its use as a tool to develop innovative algorithms and architecture to solve previously intractable problems.

VLSI Design answers not only the question of "what is VLSI," but also shows how to use VLSI. It provides graduate and upper level undergraduate students with a complete and congregated view of VLSI engineering.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Computer Science Systems Analysis & Design

Preface	p. v
Introduction	p. 1
VLSI Design Methodology	p. 3
VLSI Design--An Overview	p. 4
Summary	p. 23
To Probe Further	p. 24
Problems	p. 27
CMOS Logic Circuits	p. 29
nMOS Switch Model	p. 29
pMOS Switch Model	p. 32
CMOS Inverter	p. 34
CMOS Logic Structures	p. 38
Complementary Logic	p. 39
Pass-Transistor/Transmission-Gate Logic	p. 51
Summary	p. 60
To Probe Further	p. 61
Problems	p. 62
IC Layout and Fabrication	p. 69
CMOS IC Fabrication	p. 69
CMOS Design Rules	p. 78
Layout Examples	p. 84
Summary	p. 97
To Probe Further	p. 97
Problems	p. 98
CMOS Circuit Characterization	p. 101
MOSFET Theory	p. 101
Voltage Transfer Characteristic	p. 105
Circuit-Level Simulation	p. 109
Improved MOSFET Switch Model	p. 112
Resistance/Capacitance Estimation	p. 116
RC Timing Model	p. 123
Transistor Sizing	p. 126
[tau]-Model	p. 130
Driving Large Loads	p. 135
Power Dissipation	p. 138
Latch-Up	p. 140
Summary	p. 142
To Probe Further	p. 142
Problems	p. 143
Sequential Logic Circuits	p. 147
General Structure	p. 147
Asynchronous Sequential Logic Circuits	p. 150
D-Latch	p. 153
D-Flip-Flop	p. 157
One-Phase Clock Systems	p. 159
Two-Phase, Non-Overlapping Clock Systems	p. 160
Clock Distribution	p. 164
Sequential Circuit Design	p. 165
Summary	p. 169
To Probe Further	p. 170
Problems	p. 170
Alternative Logic Structures	p. 175
Complementary Logic Circuits	p. 175
Pass-Transistor/Transmission-Gate Logic	p. 176
Pseudo-nMOS Logic	p. 177
Programmable Logic Array	p. 182
Dynamic CMOS Logic	p. 185
Domino Logic	p. 190
Dynamic Memory Elements	p. 192
BiCMOS Logic Circuits	p. 193
Summary	p. 194
To Probe Further	p. 195
Problems	p. 196
Sub-System Design	p. 199
Adders	p. 200
Full Adder Tree	p. 209
Parallel Multipliers	p. 211
Read-Only Memory	p. 219
Random Access Memory	p. 221
Summary	p. 225
To Probe Further	p. 225
Problems	p. 226
Chip Design	p. 229
Microprocessor Design Project	p. 230
Field Programmable Gate Array	p. 244
Summary	p. 250
To Probe Further	p. 251
Problems	p. 251
Testing	p. 253
Fault Models	p. 255
Test Generation (Stuck-at Faults)	p. 258
Path Sensitization	p. 261
D-Algorithm	p. 262
Test Generation for Other Fault Models	p. 266
Test Generation Example	p. 267
Sequential Circuit Testing	p. 270
Design-for-Testability	p. 271
Built-In Self-Test	p. 272
Summary	p. 277
To Probe Further	p. 277
Problems	p. 278
Physical Design Automation	p. 281
Layout Generators and Editors	p. 281
Placement and Routing	p. 283
Floorplanning and Placement	p. 283
Routing	p. 290
Summary	p. 305
To Probe Further	p. 306
Problems	p. 308
Parallel Structures	p. 311
Parallel Architectures	p. 311
Interconnection Networks	p. 314
Pipelining	p. 322
Pipeline Scheduling	p. 326
Parallel Algorithms	p. 329
Summary	p. 336
To Probe Further	p. 337
Problems	p. 337
Array Processors	p. 341
Array Processing Examples	p. 342
Array Processor Design	p. 348
Wavefront Array Processor	p. 365
To Probe Further	p. 374
Problems	p. 375
Fault Tolerant Vlsi Architectures	p. 377
Reliability	p. 377
Fault Tolerant Design	p. 381
Fault Tolerant VLSI Arrays	p. 382
Set Replacement Algorithm	p. 383
Shifting Replacement Algorithm	p. 387
Fault Stealing Replacement Algorithm	p. 389
Compensation Path Replacement Algorithm	p. 392
Summary	p. 393
To Probe Further	p. 394
Problems	p. 395
Index	p. 397
Table of Contents provided by Syndetics. All Rights Reserved.

VLSI Design

At a Glance

Hardcover

Shipping

How to return your order

Defective items

You Can Find This Book In

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