Extreme Statistics in Nanoscale Memory Design

Cover -- Extreme Statistics in Nanoscale Memory Design -- Preface -- Contents -- Contributors -- Chapter 1: Introduction -- 1.1 Yield-Driven Design: Need for Accurate Yield Estimation -- 1.2 The Case of High-Replication Circuits -- 1.3 Why Does Standard Monte Carlo Not Work? -- 1.3.1 Process Variation Statistics: Prerequisites for Statistical Analysis -- 1.3.2 Monte Carlo Simulation -- 1.3.3 The Problem with Memories -- 1.4 An Overview of This Book -- References -- Chapter 2: Extreme Statistics in Memories -- 2.1 Cell Failure Probability: An Extreme Statistic -- 2.1.1 Units of Failure Probability -- 2.1.2 An Example of Extreme Statistics in Memories -- 2.2 Incorporating Redundancy -- 2.2.1 The Poisson Yield Model -- Reference -- Chapter 3: Statistical Nano CMOS Variability and Its Impact on SRAM -- 3.1 Introduction -- 3.2 Process Variability Classification -- 3.3 Sources of Statistical Variability -- 3.4 Statistical Aspects of Reliability -- 3.5 Gate Leakage Variability -- 3.6 Simulation of Statistical Variability -- 3.7 Simulation of Statistical Reliability -- 3.8 Variability in Future Technology Generations -- 3.9 Compact Model Strategies for Statistical Variability -- 3.10 Basics of Statistical Circuit Simulations in the Presence of Statistical Variability -- 3.11 Conclusions -- References -- Chapter 4: Importance Sampling-Based Estimation -- 4.1 Introduction -- 4.2 Statistical Sampling -- 4.2.1 Probability and Statistics: A History in the Making -- 4.2.2 Overview of Sampling Methods -- 4.2.3 Random Sample Generation -- 4.3 Monte Carlo Methods -- 4.3.1 The Beginning -- 4.3.2 Numerical Integration -- 4.3.3 Statistical Inference -- 4.3.4 Rare Event Estimation and Monte Carlo -- 4.4 Variance Reduction and Importance Sampling -- 4.4.1 An Overview of Variance Reduction Methods -- 4.4.2 Importance Sampling -- 4.5 Importance Sampling for Memory Design -- 4.5.1 The Importance Sampling Distribution -- 4.5.2 SRAM Application -- 4.6 Conclusions -- References -- Chapter 5: Direct SRAM Operation Margin Computation with Random Skews of Device Characteristics -- 5.1 Introduction -- 5.2 General Metrics for SRAM Operation Margins -- 5.3 Idealization of Statistical Chaos in Single Variable -- 5.4 Formulation of the Direct Computation for SRAM Margins -- 5.5 Example ADM and WRM Computation -- 5.6 Extending DC Computation to Transient Operations -- 5.7 Unstable SRAM Cells at High Vdd and High Beta Ratio -- 5.8 Write Fail from New Floating Bodies -- 5.9 General Transient Margin Computation Sequence and DC Margin Bias Setting -- 5.10 Thinner Tinv to Mitigate Floating Body Effects Which Degrade SRAM Stability -- 5.11 SRAM Wear and Tear from NBTI and PBTI -- 5.12 SRAM Vmax Problem from DIBL -- 5.13 Getting Around Curvatures of Metric Gradients -- 5.14 Conclusion and Acknowledgment -- Appendix: SRAM Margins to Meet Yield Targets -- References -- Chapter 6: Yield Estimation by Computing Probabilistic Hypervolumes -- 6.1 Introduction: Parameter Variations and Yield Estimation -- 6.1.1 Yield Estimation -- 6.1.2 An Example: SRAM Read Access Failure -- 6.2 Approaches to Yield Estimation -- 6.2.1 Statistical Methods -- 6.2.2 Deterministic/Mixed Methods -- 6.3 Computing the Boundary and Probabilistic Hypervolumes -- 6.3.1 Basic Idea and Geometrical Explanation -- 6.3.2 YENSS Algorithm Outline -- 6.3.3 Implicit Formu.