Hardware Verification with System Verilog

Cover -- Contents -- Preface -- Acknowledgments -- Chapter 1: Introduction -- Background -- What is Functional Verification? -- Why Focus on SystemVerilog? -- A Tour of the Handbook -- For Further Reading -- Part I: SystemVerilog and Verification (The Why and How) -- Chapter 2: Why SystemVerilog? -- Overview -- SystemVerilog as a Verification Language -- Main Benefits of Using SystemVerilog -- Drawbacks of Using SystemVerilog -- SystemVerilog Traps and Pitfalls -- Summary -- For Further Reading -- Chapter 3: OOP and SystemVerilog -- Overview -- The Evolution of OOP and SystemVerilog -- The Evolution of Functional Verification -- OOP and SystemVerilog -- Summary -- For Further Reading -- Chapter 4: A Layered Approach -- Overview -- A Whiteboard Drawing -- The "Common-Currency" Components -- The Component Layer in Detail -- The Top-Layer Components -- What is a Test? -- The Test Component -- The Test Irritator -- A Complete Test -- Summary -- For Further Reading -- Part II: An Open-Source Environment with SystemVerilog -- Chapter 5: Teal Basics -- Overview -- Teal's Main Components -- Using Teal -- Logging Output -- Using Test Parameters -- Accessing Memory -- Constrained Random Numbers -- Working with Simulation Events -- Summary -- Chapter 6: Truss: A Standard Verification Framework -- Overview -- General Considerations -- Major Classes and Their Roles -- The verification_component Virtual Base Class -- Detailed Responsibilities of the Major Components -- Test Component and Irritator Classes -- Summary -- Chapter 7: Truss Flow -- Overview -- About truss_verification_top.sv -- The Test Component Dance -- The Irritator Dance -- Compiling and Running Tests -- The First Test: A Directed Test -- The Second Test: Adding Channels and Random Parameters -- The Remaining Tests: Mix-and-Match Test Components -- Summary -- Chapter 8: Truss Example -- Overview -- Directory Structure -- Theory of Operation -- Running the Simple ALU Example -- Points of Interest -- Power-on Reset -- Driver and Monitor Protocol -- The alu_test_component -- Checking the Chip -- Completing the Test -- Summary -- Part III: Using OOP for Verification (Best Practices) -- Chapter 9: Thinking OOP -- Overview -- Sources of Complexity -- Creating Adaptable Code -- Architectural Considerations to Maximize Adaptability -- Separating Interface from Implementation -- Code Interface, Implementation, and Base Classes -- Summary -- For Further Reading -- Chapter 10: Designing with OOP -- Overview -- Keeping the Abstraction Level Consistent -- Using "Correct by Construction" -- The Value of Packages -- Data Duplication-A Necessary Evil -- Designing Well, Optimizing Only When Necessary -- Using the Protocol, Only the Protocol -- Verification Close to the Programming Model -- The Three Parts of Checking -- Separating the Test from the Testbench -- Summary -- For Further Reading -- Chapter 11: OOP Classes -- Overview -- Defining Classes -- How Much Electricity? -- Global S.