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Low-Power Variation-Tolerant Design in Nanometer Silicon - Swarup Bhunia

Low-Power Variation-Tolerant Design in Nanometer Silicon

By: Swarup Bhunia

eText | 10 November 2010

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Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

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Non-FictionEngineering & TechnologyElectronics & Communications EngineeringElectronics EngineeringCircuits & ComponentsTechnology in GeneralEngineering in GeneralComputing & I.T.Graphical & Digital Media ApplicationsComputer-Aided Design CAD

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